Patents by Inventor Wei-Shan Liao

Wei-Shan Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250092555
    Abstract: A manufacturing method of a roughened copper foil includes the following steps. A copper foil is provided. An electrolytic process is performed to form a roughening layer on the copper foil. An electrolyte solution in the electrolysis process includes copper ions in a range from 0.1 g/L to 20 g/L, sulfate ions in a range from 30 g/L to 120 g/L, and a coordination compound in a range from 0.1 g/L to 10 g/L.
    Type: Application
    Filed: October 25, 2023
    Publication date: March 20, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Yu-Chi Hsieh, Chia-Shan Chang
  • Publication number: 20250096254
    Abstract: A lithium battery positive material includes lithium nickel manganese oxide (LNMO) doped with copper, titanium, nitrogen, and carbon. In addition, a manufacturing method of the lithium battery positive material is also provided.
    Type: Application
    Filed: October 26, 2023
    Publication date: March 20, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Chia-Shan Chang, Yu-Chi Hsieh
  • Publication number: 20250092554
    Abstract: A release carrier structure includes a carrier layer, a first release layer, and a second release layer. A weight ratio of organic matter in the second release layer is greater than a weight ratio of organic matter in the first release layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 20, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Yu-Chi Hsieh, Chia-Shan Chang
  • Publication number: 20250073667
    Abstract: A complex ionic compound includes a carrier, a bridging agent, and an adsorbent. The bridging agent is grafted to the carrier, and the adsorbent is grafted to the bridging agent.
    Type: Application
    Filed: October 22, 2023
    Publication date: March 6, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Chia-Shan Chang, Yu-lin Li
  • Publication number: 20250066899
    Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
  • Patent number: 9590039
    Abstract: A semiconductor structure and a method for forming same are provided. The semiconductor structure includes a bipolar transistor. The bipolar transistor includes a base doped contact, an emitter doped contact, a collector doped contact, and well regions. The base doped contact, the emitter doped contact and the collector doped contact are formed in the different well regions having different dopant conditions from each other.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Wei-Shan Liao
  • Patent number: 9455319
    Abstract: A semiconductor device and an operating method of the same are disclosed. The semiconductor device includes a substrate, a source region, a drain region, a gate structure, a first lightly-doped region, and a first isolation region. The source region and the drain region are formed in the substrate. The gate structure is formed on the substrate and between the source region and the drain region. The first lightly-doped region is formed below the source region. The first isolation region is formed in the substrate and surrounding the source region, the drain region, and the first lightly-doped region. The source region and the drain region have a first-polarity, and the first lightly-doped region and the first isolation region have a second-polarity.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Wei-Shan Liao
  • Patent number: 9202939
    Abstract: A Schottky diode is disclosed. The Schottky diode includes: a substrate, a first-type buried layer in the substrate, a cathode region, an anode region surrounding the cathode region, and a first-type guard ring surrounding the anode region and connected to the first-type buried layer. The cathode region preferably includes a high-voltage second-type lightly doped drain in the substrate, a first-type well surrounding the high-voltage second-type lightly doped drain, and a first-type doping region in the first-type well and surrounding the high-voltage second-type lightly doped drain.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: December 1, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Wei-Shan Liao
  • Publication number: 20150325639
    Abstract: A semiconductor device and an operating method of the same are disclosed. The semiconductor device includes a substrate, a source region, a drain region, a gate structure, a first lightly-doped region, and a first isolation region. The source region and the drain region are formed in the substrate. The gate structure is formed on the substrate and between the source region and the drain region. The first lightly-doped region is formed below the source region. The first isolation region is formed in the substrate and surrounding the source region, the drain region, and the first lightly-doped region. The source region and the drain region have a first-polarity, and the first lightly-doped region and the first isolation region have a second-polarity.
    Type: Application
    Filed: May 12, 2014
    Publication date: November 12, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Wei-Shan Liao
  • Publication number: 20150228808
    Abstract: A Schottky diode is disclosed. The Schottky diode includes: a substrate, a first-type buried layer in the substrate, a cathode region, an anode region surrounding the cathode region, and a first-type guard ring surrounding the anode region and connected to the first-type buried layer. The cathode region preferably includes a high-voltage second-type lightly doped drain in the substrate, a first-type well surrounding the high-voltage second-type lightly doped drain, and a first-type doping region in the first-type well and surrounding the high-voltage second-type lightly doped drain.
    Type: Application
    Filed: February 11, 2014
    Publication date: August 13, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Wei-Shan Liao
  • Publication number: 20150179779
    Abstract: A semiconductor structure and a method for forming same are provided. The semiconductor structure includes a bipolar transistor. The bipolar transistor includes a base doped contact, an emitter doped contact, a collector doped contact, and well regions. The base doped contact, the emitter doped contact and the collector doped contact are formed in the different well regions having different dopant conditions from each other.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Wei-Shan Liao
  • Patent number: 8803235
    Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
  • Patent number: 8786362
    Abstract: A Schottky diode having a current leakage protection structure includes a Schottky diode unit, a first isolation portion and a second isolation portion. The Schottky diode unit is defined in a substrate and includes a metalized anode, an active region having dopants of first conductive type, a cathode and at least one isolation structure. The first isolation portion having dopants of second conductive type is formed between substrate and active region, and the first isolation portion includes a first well disposed beneath active region, and a first guard ring surrounding active region and connecting to the first well. The second isolation portion having dopants of first conductive type is formed between substrate and the first isolation portion, and the second isolation portion includes a second well disposed beneath the first well, and a second guard ring surrounding the first guard ring and connecting to the second well.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: July 22, 2014
    Assignee: United Microelectronics Corporation
    Inventors: An-Hung Lin, Wei-Shan Liao, Bo-Jui Huang, Hong-Ze Lin, Ting-Zhou Yan, Wen-Chun Chang
  • Publication number: 20140048877
    Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 20, 2014
    Inventors: Wei-Shan LIAO, An-Hung LIN, Hong-Ze LIN, Bo-Jui HUANG
  • Publication number: 20140035034
    Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 6, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
  • Patent number: 8643104
    Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Shan Liao, An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang
  • Patent number: 8587058
    Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.
    Type: Grant
    Filed: January 2, 2012
    Date of Patent: November 19, 2013
    Assignee: United Microelectronics Corp.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
  • Patent number: 8581338
    Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: November 12, 2013
    Assignee: United Microelectronics Corp.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
  • Patent number: 8482063
    Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 9, 2013
    Assignee: United Microelectronics Corporation
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
  • Publication number: 20130168767
    Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.
    Type: Application
    Filed: January 2, 2012
    Publication date: July 4, 2013
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian