Patents by Inventor Wei-Sheng Yu

Wei-Sheng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10783818
    Abstract: A dual gate transistor circuit, a pixel circuit, and a gate drive circuit are provided. The dual gate transistor circuit includes a dual gate transistor, a first diode, and a second diode. The dual gate transistor has a first gate and a second gate, and the first gate receives a drive signal. The first diode is connected in series between the first gate and the second gate according to a first-polarity direction. The second diode is connected in series between the first gate and the second gate according to a second-polarity direction. The first-polarity direction is opposite to the second-polarity direction.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 22, 2020
    Assignee: Au Optronics Corporation
    Inventors: Shu-Wei Tsao, Chi-Jui Lin, Shu-Feng Wu, Wei-Sheng Yu
  • Publication number: 20200035139
    Abstract: A dual gate transistor circuit, a pixel circuit, and a gate drive circuit are provided. The dual gate transistor circuit includes a dual gate transistor, a first diode, and a second diode. The dual gate transistor has a first gate and a second gate, and the first gate receives a drive signal. The first diode is connected in series between the first gate and the second gate according to a first-polarity direction. The second diode is connected in series between the first gate and the second gate according to a second-polarity direction. The first-polarity direction is opposite to the second-polarity direction.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 30, 2020
    Applicant: Au Optronics Corporation
    Inventors: Shu-Wei Tsao, Chi-Jui Lin, Shu-Feng Wu, Wei-Sheng Yu
  • Patent number: 9046726
    Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: June 2, 2015
    Assignee: Au Optronics Corporation
    Inventors: Hsiao-Wei Cheng, Sung-Hui Lin, Ming-Yung Huang, Pin-Miao Liu, Wen-Shin Wu, Chun-Yao Huang, Wei-Sheng Yu
  • Patent number: 9025098
    Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: May 5, 2015
    Assignee: Au Optronics Corporation
    Inventors: Hsiao-Wei Cheng, Sung-Hui Lin, Ming-Yung Huang, Pin-Miao Liu, Wen-Shin Wu, Chun-Yao Huang, Wei-Sheng Yu
  • Publication number: 20140313466
    Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventors: Hsiao-Wei Cheng, Sung-Hui Lin, Ming-Yung Huang, Pin-Miao Liu, Wen-Shin Wu, Chun-Yao Huang, Wei-Sheng Yu
  • Publication number: 20140313467
    Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventors: Hsiao-Wei Cheng, Sung-Hui Lin, Ming-Yung Huang, Pin-Miao Liu, Wen-Shin Wu, Chun-Yao Huang, Wei-Sheng Yu
  • Patent number: 8804059
    Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: August 12, 2014
    Assignee: Au Optronics Corporation
    Inventors: Hsiao-Wei Cheng, Sung-Hui Lin, Ming-Yung Huang, Pin-Miao Liu, Wen-Shin Wu, Chun-Yao Huang, Wei-Sheng Yu
  • Patent number: 8421079
    Abstract: A pixel structure having an SMII (semiconductor-metal-insulator-ITO) capacitor is provided. Specifically, a partial region of a transparent electrode layer corresponding to a semiconductor layer is removed, so as to eliminate parasitic capacitance between the transparent electrode layer and the semiconductor layer, prevent defects (e.g., waterfall, image sticking, etc.) from occurring on the display frame, and improve the display quality.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: April 16, 2013
    Assignee: Au Optronics Corporation
    Inventors: Chia-Ming Chang, Wei-Sheng Yu, Ming-Hao Chang
  • Publication number: 20120161135
    Abstract: A pixel structure having an SMII (semiconductor-metal-insulator-ITO) capacitor is provided. Specifically, a partial region of a transparent electrode layer corresponding to a semiconductor layer is removed, so as to eliminate parasitic capacitance between the transparent electrode layer and the semiconductor layer, prevent defects (e.g., waterfall, image sticking, etc.) from occurring on the display frame, and improve the display quality.
    Type: Application
    Filed: April 27, 2011
    Publication date: June 28, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chia-Ming Chang, Wei-Sheng Yu, Ming-Hao Chang
  • Publication number: 20120092605
    Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
    Type: Application
    Filed: February 11, 2011
    Publication date: April 19, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hsiao-Wei Cheng, Sung-Hui Lin, Ming-Yung Huang, Pin-Miao Liu, Wen-Shin Wu, Chun-Yao Huang, Wei-Sheng Yu
  • Patent number: 7842954
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: November 30, 2010
    Assignee: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin
  • Publication number: 20100213464
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 26, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin
  • Patent number: 7763480
    Abstract: A method for manufacturing a thin film transistor (TFT) array substrate needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain. Thus, the difficulty of the manufacturing process is effectively reduced.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: July 27, 2010
    Assignee: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Chien-Hung Chen
  • Patent number: 7754547
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 13, 2010
    Assignee: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin
  • Patent number: 7612394
    Abstract: A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: November 3, 2009
    Assignee: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Chien-Hung Chen
  • Publication number: 20090173943
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Application
    Filed: April 14, 2008
    Publication date: July 9, 2009
    Applicant: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin
  • Publication number: 20090142864
    Abstract: A method for manufacturing a thin film transistor (TFT) array substrate needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain. Thus, the difficulty of the manufacturing process is effectively reduced.
    Type: Application
    Filed: February 12, 2009
    Publication date: June 4, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Wei-Sheng Yu, Chien-Hung Chen
  • Publication number: 20080116787
    Abstract: A pixel structure of active matrix organic light emitting display and method for fabricating the same are provided. In the method, a transparent electrode, an organic light emitting diode, and a reflective electrode are formed on a substrate. Subsequently, at least one switching thin film transistor, at least one driving thin film transistor, a scan line, a data line, and a storage capacitor are formed over the substrate.
    Type: Application
    Filed: March 9, 2007
    Publication date: May 22, 2008
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Shien-Chi Hsu, Chin-Yuan Lin, Wei-Sheng Yu, Yi-Jun Lu, Shu-Ching Hsu
  • Publication number: 20070292998
    Abstract: A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.
    Type: Application
    Filed: November 10, 2006
    Publication date: December 20, 2007
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Wei-Sheng Yu, Chien-Hung Chen