Abstract: A photo mask for an extreme ultraviolet (EUV) lithography includes a mask alignment mark for aligning the photo mask to an EUV lithography tool, and sub-resolution assist patterns disposed around the mask alignment mark. A dimension of the sub-resolution assist patterns is in a range from 10 nm to 50 nm.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.

Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.

Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: A chip packaging structure includes a flexible circuit board, a first built-up structure, a second built-up structure, and a first solder resist layer. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer. The first dielectric layer includes a first conductive pattern, a bearing layer opposite to the first conductive pattern and corresponding to the laminated area. The first built-up structure is located on the first conductive pattern and corresponds to the laminated area, and includes a second dielectric layer and a second conductive pattern electrically connected with the first conductive pattern. The second built-up structure is located on the bearing layer and corresponds to the laminated area, and includes a third dielectric layer and a third conductive pattern electrically connected with the first conductive pattern. The first solder resist layer covers the second conductive pattern.

Abstract: A chip packaging structure includes a flexible circuit board, a first built-up structure, a second built-up structure, and a first solder resist layer. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer. The first dielectric layer includes a first conductive pattern, a bearing layer opposite to the first conductive pattern and corresponding to the laminated area. The first built-up structure is located on the first conductive pattern and corresponds to the laminated area, and includes a second dielectric layer and a second conductive pattern electrically connected with the first conductive pattern. The second built-up structure is located on the bearing layer and corresponds to the laminated area, and includes a third dielectric layer and a third conductive pattern electrically connected with the first conductive pattern. The first solder resist layer covers the second conductive pattern.

Abstract: A printed circuit board includes a base layer, a first conductive pattern, and a first surface treatment patterned layer formed on a portion of a surface of the first conductive pattern. The first conductive pattern includes a first copper foil layer on one side of the base layer and a first conductive layer on a portion of a surface of the first copper foil layer. The first conductive pattern which is covered by the first surface treatment patterned layer has sidewalls obliquely tilted with respect to the base layer. The first conductive pattern covered with the first surface treatment patterned layer has a cross section that is trapezoidal shaped, and a width which gradually decreases from the base layer to the first conductive layer.

Abstract: A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer, a first conductive pattern and a bearing layer located at opposite sides. The bearing layer corresponds to the laminated area. A second dielectric layer and a second conductive pattern are formed on the first conductive pattern. A third dielectric layer and a third conductive pattern are formed on the bearing layer. All of the second and third dielectric layers, and the second and third conductive pattern corresponds to the laminated area. A first solder resist layer is formed on the second conductive layer. The first solder resist layer defines a plurality of openings, a portion of the second conductive pattern is exposed from the openings defining a plurality of first pads.

Abstract: The present disclosure relates to a method for manufacturing a printed circuit board. The method includes the steps as follows. First, a substrate including a base layer and a copper foil layer on a surface of the base layer is provided. Second, a conductive layer is formed on portions of the copper foil layer. Third, portions of the copper foil layer exposed from the conductive layer are removed by an etching process, and the conductive layer is thinner by the etching process. The reserved portions of the copper foil layer and the conductive layer form a conductive pattern to obtain a printed circuit board without plating wires. A printed circuit board without plating wires made by the above method is also provided.

Abstract: A chip package can include a chip, a plurality of metal posts, an encapsulating body and a redistribution layer. The plurality of metal posts surrounds the chip. The encapsulating body surrounds the chip and the plurality of metal posts. The redistribution layer is coupled to the encapsulating body and electrically coupled to the chip and the plurality of metal posts. A method for manufacturing the chip package is also provided.

Abstract: The present disclosure relates to a method for manufacturing a printed circuit board. The method includes the steps as follows. First, a substrate including a base layer and a copper foil layer on a surface of the base layer is provided. Second, a conductive layer is formed on portions of the copper foil layer. Third, portions of the copper foil layer exposed from the conductive layer are removed by an etching process, and the conductive layer is thinner by the etching process. The reserved portions of the copper foil layer and the conductive layer forms a conductive pattern to obtain a printed circuit board without plating wires. A printed circuit board without plating wires made by the above method is also provided.

Abstract: A method for manufacturing a packaging substrate includes: patterning a first photo-resisting layer having first openings on a copper foil layer to expose portions of the copper foil layer; patterning a removable second photo-resisting layer having second openings on the first photo-resisting layer to expose the first openings; filling copper into the first and second openings to form base portions and a first wiring layer; orderly forming a first dielectric layer and a second wiring layer on the first wiring layer; patterning a removable third photo-resisting layer comprising covering portions opposite to the base portions on the copper foil layer; and etching the copper foil layer to form protruding portions connected to and corresponding to the base portions to define a copper pillar bump, a size of the copper pillar bump gradually increasing from the protruding portions to the base portions.

Abstract: A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer, a first conductive pattern and a bearing layer located at opposite sides. The bearing layer corresponds to the laminated area. A second dielectric layer and a second conductive pattern are formed on the first conductive pattern. A third dielectric layer and a third conductive pattern are formed on the bearing layer. All of the second and third dielectric layers, and the second and third conductive pattern corresponds to the laminated area. A first solder resist layer is formed on the second conductive layer. The first solder resist layer defines a plurality of openings, a portion of the second conductive pattern is exposed from the openings defining a plurality of first pads.

Abstract: A method for manufacturing a packaging substrate includes: patterning a first photo-resisting layer having first openings on a copper foil layer to expose portions of the copper foil layer; patterning a removable second photo-resisting layer having second openings on the first photo-resisting layer to expose the first openings; filling copper into the first and second openings to form base portions and a first wiring layer; orderly forming a first dielectric layer and a second wiring layer on the first wiring layer; patterning a removable third photo-resisting layer comprising covering portions opposite to the base portions on the copper foil layer; and etching the copper foil layer to form protruding portions connected to and corresponding to the base portions to define a copper pillar bump, a size of the copper pillar bump gradually increasing from the protruding portions to the base portions.