Patents by Inventor Wei-Son Tsai

Wei-Son Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791300
    Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 17, 2023
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Chia-Yu Kuo, Pei-Geng Weng, Wei-Son Tsai, Yih-Jenn Jiang
  • Publication number: 20230066456
    Abstract: A substrate structure is provided with a first electrical contact pad formed on an insulating layer of a substrate body, where the first electrical contact pad includes a first pad portion disposed on the insulating layer and at least one first protruding portion embedded in the insulating layer, so that the first pad portion is electrically connected to a circuit layer in the insulating layer by a conductive blind via, and the first protruding portion is free from being electrically connected to the circuit layer, such that, through a design of the first protruding portion, all surfaces of a metal layer formed on the insulating layer can meet the requirement of coplanarity.
    Type: Application
    Filed: June 14, 2022
    Publication date: March 2, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Pei-Geng Weng, Fang-Lin Tsai, Wei-Son Tsai, Yih-Jenn Jiang
  • Publication number: 20220148996
    Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 12, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Chia-Yu Kuo, Pei-Geng Weng, Wei-Son Tsai, Yih-Jenn Jiang