Patents by Inventor Wei-Son Tsai

Wei-Son Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250226312
    Abstract: The present disclosure provides a circuit structure having an insulating layer; a plurality of first circuits disposed on one side of the insulating layer; and a plurality of first electrical connection pads, each having a first extension portion extending toward and electrically connected to one end of a first circuit of the first circuits, wherein a width of the extension portion gradually decreases toward a junction of the first extension portion and the first circuit. By implementing of the present disclosure, stress on the junction between the electrical connection pad and the circuit can be dispersed along the extension portion through the arrangement of the extension portion and its tapered width design, thereby preventing fracture on the junction of the electrical connection pad and the circuit due to excessively concentrated stress, so that the manufacturing yield and reliability of semiconductor packages with this circuit structure can be improved.
    Type: Application
    Filed: July 10, 2024
    Publication date: July 10, 2025
    Inventors: Hsing-Yu LIU, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG
  • Publication number: 20240312889
    Abstract: An electronic package and a circuit structure thereof are provided, in which a circuit layer and an electrical function part are formed on a dielectric layer of the circuit structure, and the dielectric layer has at least one corner at a right angle, where a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape, so that stress concentration can be reduced, thereby preventing the electronic package from warping.
    Type: Application
    Filed: June 30, 2023
    Publication date: September 19, 2024
    Inventors: Fang-Lin TSAI, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG, Ching-Hung TSENG
  • Publication number: 20240282655
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is pasted on a routing layer that is configured with a plurality of conductive pillars, then the electronic element, the conductive pillars and the routing layer are covered with a cladding layer, and a circuit structure electrically connected to the electronic element and the conductive pillars is formed on the cladding layer. Therefore, the conductive pillars can be directly formed on the routing layer and the dielectric layer is omitted, so there is no need to consider the thickness of the dielectric layer, so as to facilitate the thinning of the electronic package.
    Type: Application
    Filed: June 1, 2023
    Publication date: August 22, 2024
    Inventors: Fang-Lin TSAI, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG, Sheng-Hua YANG
  • Publication number: 20240266335
    Abstract: An electronic package and the manufacturing method thereof are provided, in which a first electronic element and a second electronic element are disposed on a carrier structure, and the first electronic element and the second electronic element are electrically connected to each other by a wire. Therefore, by replacing some layers of the circuit layer of the carrier structure with the wire, the carrier structure can satisfy the functional signal transmission of the first and second electronic elements without configuring too many circuit layers, so as to shorten the process steps and time of the carrier structure, thereby effectively reducing the manufacturing cost of the electronic package.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 8, 2024
    Inventors: Huan-Shiang LI, Yih-Jenn JIANG, Cheng-Kai CHANG, Wei-Son TSAI, Yi-Chieh WANG
  • Publication number: 20240222290
    Abstract: An electronic package is provided, in which an electronic element and a plurality of shielding pillars are embedded in an encapsulating layer, a shielding layer is formed on one surface of the encapsulating layer to cover the electronic element and is in contact with and connected to the plurality of shielding pillars, and a circuit structure is formed on the other surface of the encapsulating layer to electrically connect to the electronic element. Therefore, when the electronic package is disposed on a circuit board, the design of the shielding layer and the plurality of shielding pillars can provide the electronic element with heat dissipation and shielding effects without a metal cover arranged on the electronic element.
    Type: Application
    Filed: May 2, 2023
    Publication date: July 4, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin TSAI, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG, Ching-Hung TSENG
  • Patent number: 11791300
    Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 17, 2023
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Chia-Yu Kuo, Pei-Geng Weng, Wei-Son Tsai, Yih-Jenn Jiang
  • Publication number: 20230066456
    Abstract: A substrate structure is provided with a first electrical contact pad formed on an insulating layer of a substrate body, where the first electrical contact pad includes a first pad portion disposed on the insulating layer and at least one first protruding portion embedded in the insulating layer, so that the first pad portion is electrically connected to a circuit layer in the insulating layer by a conductive blind via, and the first protruding portion is free from being electrically connected to the circuit layer, such that, through a design of the first protruding portion, all surfaces of a metal layer formed on the insulating layer can meet the requirement of coplanarity.
    Type: Application
    Filed: June 14, 2022
    Publication date: March 2, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Pei-Geng Weng, Fang-Lin Tsai, Wei-Son Tsai, Yih-Jenn Jiang
  • Publication number: 20220148996
    Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 12, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Chia-Yu Kuo, Pei-Geng Weng, Wei-Son Tsai, Yih-Jenn Jiang