Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.

Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.

Abstract: An ESD protection circuit includes a buffer circuit, a driving circuit, and a power-clamping circuit. The buffer circuit includes first and second transistors having a first conductivity type coupled in a cascade configuration between a first node and a first power supply node. A bonding pad is coupled to the first node. The drive circuit determines a state of at least one of the first and second transistors according to a control voltage. The drive circuit includes a third transistor having a second conductivity type, which is coupled between a second power supply node and a gate of the first transistor and is controlled by the control signal. The power-clamping circuit is coupled to the bonding pad and a gate of the third transistor at a second node. The control voltage is generated at the second node and determined by a voltage at the bonding pad.

Abstract: An integral-type reaction cartridge includes a plurality of reaction containers and at least a separation container. The plural reaction containers and the separation container are integrally formed of plastic and lined along a first direction. The separation container has a first end, a second end opposing the first end, and a hollow accommodating space between the first and second ends, wherein the first end is an open end, the second end is a closed end, and the accommodating space tapers from the first end to the second end. The accommodating space has a first side and a second side along the first direction, as well as a third side and a fourth side along a second direction perpendicular to the first direction. Near the second end, at least one of the first side and the second side has a greater slope than the third side and the fourth side.

Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line.

Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a substrate having a first conductive type. A first transistor, a second transistor and a select transistor having a second conductive type are disposed in the substrate, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. A source region of the first transistor is coupled to a bit line. A drain region of the second transistor and a gate of the select transistor are coupled to a select gate line. A drain region of the first transistor is coupled to a source region of the select transistor. A drain region of the select transistor is coupled to a select line.

Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line.

Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a substrate having a first conductive type. A first transistor, a second transistor and a select transistor having a second conductive type are disposed in the substrate, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. A source region of the first transistor is coupled to a bit line. A drain region of the second transistor and a gate of the select transistor are coupled to a select gate line. A drain region of the first transistor is coupled to a source region of the select transistor. A drain region of the select transistor is coupled to a select line. A bit is stored in the first and second gates by controlling the bit line and the select gate line. A bit stored in the first and second gates is erased by controlling the bit line and the select gate line.

Abstract: An integral-type reaction cartridge includes a plurality of reaction containers and at least a separation container. The plural reaction containers and the separation container are integrally formed of plastic and lined along a first direction. The separation container has a first end, a second end opposing the first end, and a hollow accommodating space between the first and second ends, wherein the first end is an open end, the second end is a closed end, and the accommodating space tapers from the first end to the second end. The accommodating space has a first side and a second side along the first direction, as well as a third side and a fourth side along a second direction perpendicular to the first direction. Near the second end, at least one of the first side and the second side has a greater slope than the third side and the fourth side.

Abstract: A manufacturing method of an artificial strip for imitative rattan/willow furniture is to mix unicolor or multicolor polyethylene (PE) with a catalyst that makes the mixture foam after heating. Then, the mixture is extruded via special shaped opening on a shaping mold to perform the artificial strip with chap and crank patterns. Moreover, the color distribution on the artificial strip can be performed evenly or unevenly to create more versatile appearance. Thereby, the artificial strip has a verisimilitude texture approximately like the natural willow or rattan strips to make the manufactured imitative rattan/willow furniture have excellent appearance.

Abstract: A manufacturing method of an artificial strip for imitated rattan furniture is completed by steps of: inputting polyester plastic material with one color or two colors into at least one plastic extruder; thermal-melting the polyester plastic material to pour into a shaping molds, extruding the melted polyester plastic material in form of a continuous geometry strip so that the strip has at least one color on its surface; cooling the strip; twisting the strip to perform spiral wavy surface to enhance vivid appearance. Lastly, the strip is reeled up to achieve an annular bundle. Thereby, the artificial strip has a verisimilitude texture approximately like the natural willow or rattan strips to make the manufactured imitated rattan/willow furniture have excellent appearance. A device system carries out the manufacturing method is also disclosed in this invention.