Patents by Inventor Wei-Ta WANG

Wei-Ta WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10742902
    Abstract: A tracking system is provided. The tracking system comprises a trackable device which comprises a first illuminating module and the first illuminating module emits an infrared (IR) light and a tracking device which comprises an optical sensing module and a processor. The optical module is configured to sense an IR spectrum to capture a first image and sense a visible spectrum to capture a second image, and the IR light is in the IR spectrum. The processor is coupled to the optical sensing module. The processor is configured to search in the first image a first region corresponding to the IR light, locate in the second image a second region associated with the first region in the first image, and calculate a spatial status of the trackable device according to the second region in the second image.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: August 11, 2020
    Assignee: HTC Corporation
    Inventors: Yuan-Tung Chen, Hsu-Hong Feng, Tzu-Yin Chang, Wei-Ta Wang, Tzu-Chieh Yu
  • Publication number: 20200214642
    Abstract: A state assessment system, a diagnosis and treatment system and a method for operating the diagnosis and treatment system are disclosed. An oscillator model converts a physiological signal of a subject into a defined feature image. A classification model analyzes state information of the subject based on the feature image. An analysis model outputs a treatment suggestion for the subject based on the state information of the subject. An AR projection device projects acupoint positions of a human body onto the subject, for the subject to be treated based on the treatment suggestion.
    Type: Application
    Filed: December 19, 2019
    Publication date: July 9, 2020
    Inventors: Chii-Wann Lin, Kuo-Chun Lee, Jung-Chuan Pan, Heng-Jie Wang, Wei-Zheng Lu, Po-An Hsu, Kun-Ta Wu
  • Patent number: 10699958
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 30, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Chang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta, Ling-Gang Fang, Shang Xue
  • Publication number: 20200154565
    Abstract: A composite with hollow nano-structures comprises multiple one dimensional hollow nanowires being dispersed into a polymer film; the polymer film is flexible; a dielectric constant of the one dimensional hollow nanowire is lower than a dielectric constant of the polymer film; and a dielectric constant of the composite is between the dielectric constant of the one dimensional hollow nanowire and the dielectric constant of the polymer film.
    Type: Application
    Filed: September 19, 2019
    Publication date: May 14, 2020
    Inventors: Tzong-Ming Wu, Fuh-Sheng Shieu, Wei-Ping Dow, Hong-Ta Yang, Jie-Mao Wang, Hsiang-Ting Wang
  • Publication number: 20200144364
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Application
    Filed: December 20, 2019
    Publication date: May 7, 2020
    Inventors: Chia-Ta YU, Sheng-Chen WANG, Wei-Yuan LU, Chien-I KUO, Li-Li SU, Feng-Cheng YANG, Yen-Ming CHEN, Sai-Hooi YEONG
  • Publication number: 20200119146
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: CHENG-TA WU, YI-HSIEN LEE, WEI-MING YOU, TING-CHUN WANG
  • Patent number: 10623351
    Abstract: A messaging system and method thereof are disclosed herein. The messaging method is suitable for the messaging system, in which the messaging system includes a first electronic device and a second electronic device. The messaging method includes the following steps: determining a latest messaging task executed on the first electronic device; displaying a notification icon corresponding to an application program on a display module of the second electronic device, in which the application program is related to the latest messaging task; detecting a confirmation input corresponding to the notification icon; and launching the application program on the second electronic device according to the confirmation input.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 14, 2020
    Assignee: HTC Corporation
    Inventors: Pei-Lin Wang, Wei-Ta Pan
  • Publication number: 20200043791
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 6, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Wei-Chang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta, Ling-Gang Fang, Shang Xue
  • Patent number: 10529803
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 10504998
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang
  • Patent number: 10312249
    Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chang Liu, Zhen Chen, Shen-De Wang, Chuan Sun, Wei Ta, Wang Xiang
  • Publication number: 20190139971
    Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Wei-Chang LIU, Zhen CHEN, Shen-De WANG, Chuan SUN, Wei TA, Wang XIANG
  • Publication number: 20180332240
    Abstract: A tracking system is provided. The tracking system comprises a trackable device which comprises a first illuminating module and the first illuminating module emits an infrared (IR) light and a tracking device which comprises an optical sensing module and a processor. The optical module is configured to sense an IR spectrum to capture a first image and sense a visible spectrum to capture a second image, and the IR light is in the IR spectrum. The processor is coupled to the optical sensing module. The processor is configured to search in the first image a first region corresponding to the IR light, locate in the second image a second region associated with the first region in the first image, and calculate a spatial status of the trackable device according to the second region in the second image.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 15, 2018
    Inventors: Yuan-Tung CHEN, Hsu-Hong FENG, Tzu-Yin CHANG, Wei-Ta WANG, Tzu-Chieh YU