Patents by Inventor Wei-The Chen

Wei-The Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11419052
    Abstract: A user equipment (UE) interacts with a base station (BS) to activate a power saving mode based on a triggering condition. The UE receives reference signals (RSs) from a first RS-set of quasi-colocated (QCLd) RSs, derives a measurement result by measuring the RSs, and uses the first measurement result (and in some cases measurements results for other RS set) for evaluation of the triggering condition to identify whether the triggering condition is satisfied. The UE and the BS switch from the first RS-set to a second RS-set once the triggering condition is satisfied.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 16, 2022
    Assignee: ACER INCORPORATED
    Inventors: Wei-Chen Pao, Chien-Min Lee
  • Patent number: 11417619
    Abstract: A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a second bonding structure. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. The first dielectric layer is hybrid bonded to the second dielectric layer. The first connectors are hybrid bonded to the second connectors. The encapsulant laterally encapsulates the second die. The TIVs penetrate through the encapsulant and are connected to the first bonding structure.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh
  • Patent number: 11419123
    Abstract: Methods, systems, and devices for wireless communications are described. In some examples, a base station or other network entity may allocate uplink resources to UEs, or groups of UEs, that are subsequently reallocated. For example, a base station may determine a reallocation of uplink resources and issue a cancellation or preemption indication that may correspond to at least a portion of the previously-allocated resources (e.g., as allocated to particular UEs). UEs may be configured to monitor for cancellation or preemption indications, and based on received cancellation or preemption indications, UEs may determine whether or not to proceed with an uplink transmission using their previously-allocated uplink resources.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: August 16, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Seyed Ali Akbar Fakoorian, Seyedkianoush Hosseini, Wei Yang, Wanshi Chen
  • Patent number: 11417838
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11418012
    Abstract: A structured beam generation device based on beam shaping and a method adopting the device are provided. Linearly polarized beam emitted by a laser sequentially passes through an electro-optic intensity modulator, a half-wave plate, and a first beam expander, and then enters a first polarization beam-splitting prism to be transmitted and reflected. The transmitted beam sequentially passes through a beam shaper, an optical delay line, and a first reflector to form a parallel ring-shaped beam to be transmitted by a second polarization beam-splitting prism. The reflected beam sequentially passes through an electro-optic phase modulator, a second reflecting mirror, and a second beam expander, and is then reflected by the second polarization beam-splitting prism and combined with the transmitted beam into a beam, which is then adjusted by a polarizing plate have consistent polarization direction, and is finally focused at a focal plane by a focusing lens for interference.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 16, 2022
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Wei Gong, Ke Si, Jiajia Chen
  • Patent number: 11417599
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 11417566
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11416200
    Abstract: The disclosure relates to a display method and a display system. The display method includes: connecting a plurality of display devices in series with each other, the plurality of display devices including a main display device and at least one slave display device, the main display device having EDID; setting the connection order of the display device; correspondingly changing the EDID of the main display device according to the connection order of the display device; configuring the main display device to receive the display image according to the changed EDID; and configuring the display device to perform an image segmentation operation on the display image according to the connection order to respectively display multiple segmented regions of the display image.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 16, 2022
    Assignee: Optoma Corporation
    Inventors: Wei-Wei Yin, Jui-Chi Chen, Yen-Hsiang Hung
  • Patent number: 11418159
    Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 16, 2022
    Assignee: GRACE CONNECTION MICROELECTRONICS LIMITED
    Inventors: Pei Wei Chen, Hsien-Ku Chen
  • Patent number: 11412940
    Abstract: The present invention provides a dynamic measurement device with a blood pressure determination function, comprising: a heartbeat sensing module disposed on the chest area of a user wherein the heartbeat sensing module comprising a heart sound sensor for obtaining heartbeat signals; a pulse sensing module disposed on a limb area of the user, the pulse sensing module comprising a pulse wave sensor for obtaining pulse signals; and a data calculating module for calculating a mean arterial pressure and a value of systolic blood pressure and diastolic blood pressure based on the heartbeat signals and pulse signals. In addition to dynamically monitoring the blood pressure of a user for 24 hours, the present invention can dynamically monitor the heart sounds of the user for 24 hours individually in order to monitor user's physical condition. Therefore, the present invention has important medical meanings.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 16, 2022
    Assignees: BIV MEDICAL, LTD.
    Inventors: Shiming Lin, Shih-Wei Chiang, Cheng-Yan Guo, Tai-Cun Lin, Wei-Chih Huang, Chun-Nan Chen, Ya-Ting Chang
  • Patent number: 11416603
    Abstract: Methods, systems, articles of manufacture and apparatus to detect process hijacking are disclosed herein. An example apparatus to detect control flow anomalies includes a parsing engine to compare a target instruction pointer (TIP) address to a dynamic link library (DLL) module list, and in response to detecting a match of the TIP address to a DLL in the DLL module list, set a first portion of a normalized TIP address to a value equal to an identifier of the DLL. The example apparatus disclosed herein also includes a DLL entry point analyzer to set a second portion of the normalized TIP address based on a comparison between the TIP address and an entry point of the DLL, and a model compliance engine to generate a flow validity decision based on a comparison between (a) the first and second portion of the normalized TIP address and (b) a control flow integrity model.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Zheng Zhang, Jason Martin, Justin Gottschlich, Abhilasha Bhargav-Spantzel, Salmin Sultana, Li Chen, Wei Li, Priyam Biswas, Paul Carlson
  • Patent number: 11417610
    Abstract: A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 11416680
    Abstract: Described herein is a framework for classifying social media inputs. In accordance with one aspect of the framework, one or more social media inputs is acquired from one or more social media platforms. The social media inputs are cleaned to remove redundant elements. One or more features are extracted from the cleaned social media inputs. The social media inputs are classified by a trained classifier into predefined categories using the extracted one or more features.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: August 16, 2022
    Assignee: SAP SE
    Inventors: Danqing Cai, Wei Tah Chai, Pek Gnee Ng, Subashini Rengarajan, Xin Zheng, Hang Guo, Weile Chen
  • Patent number: 11415736
    Abstract: The present disclosure provides a backlight module including a light guide plate including a light-emitting surface, a bottom surface opposite to the light-emitting surface, and a light-incident side connecting the light-emitting surface and the bottom surface and light-emitting elements disposed at the light-incident side along a first direction. The light guide plate includes first columnar microstructures extending along a second direction perpendicular to the first direction on the light-emitting surface and columnar microstructure groups with second columnar microstructures, which are 1-15 times the number of the adjacent first columnar microstructures, between the first columnar microstructures extending along the second direction on the light-emitting surface. A first width of the first columnar microstructures is larger than or equal to a second width of the columnar microstructure groups along the first direction.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: August 16, 2022
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Yu-Huan Chiu, Chien-Wei Liao, Yen-Lung Chen
  • Patent number: 11417370
    Abstract: A method of operating a memory device is provide. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compare with a clock cycle period to determine that the power nap period is less that the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chen Lin, Wei Min Chan
  • Patent number: 11416966
    Abstract: A system for image scaling and enhancement is provided. The system includes a scaling processing unit, a deep-learning residue network unit and a combination unit. The filter scaling processing unit is configured to upscale a low-resolution image to output a high-resolution image. The deep-learning residue network unit is operated based on a deep-learning result, and configured to output a high-resolution residue image corresponding to the low-resolution image. The combination unit is configured to adjust the high-resolution residue image according to a weighting factor and combine an adjusted high-resolution residue image and the high-resolution image, in order to output an enhanced image, wherein the weighting factor is different from a reference weighting factor being used in a deep-learning procedure for training the deep-learning residue network unit.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 16, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Wei Yu, Yi-Ting Bao, Yen-Lin Chen, Shang-Yen Lin
  • Patent number: 11417587
    Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11416287
    Abstract: Embodiments of the present disclosure provide a method and a coroutine framework for processing parallel tasks, a device, a medium and an unmanned vehicle. The method includes: switching a current coroutine to a target coroutine in response to a task switching instruction, in which, the coroutine is created at a user layer for processing a task, and the coroutine at the user layer is executed by a thread at a kernel layer; and saving context of a task processed by the current coroutine, and reading context of a task processed by the target coroutine, such that the thread at the kernel layer corresponding to the target coroutine processes the task based on the context of the target coroutine when executing the target coroutine.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 16, 2022
    Assignee: Apollo Intelligent Driving Technology (Beijing) Co., Ltd.
    Inventors: Wei He, Zhuo Chen, Baisheng Wang, Kaiwen Feng, Ronggui Peng, Chao Zhang
  • Patent number: 11417651
    Abstract: A semiconductor apparatus includes first, second and third transistors integrated in a monocrystal chip. Both the first and second transistors are vertical devices, each having a source node, a gate node and a drain node. The source node of the first transistor electrically connects to a primary source pin, the source node of the second transistor to a sample pin, and the gate nodes of the first and the second transistors to a control-gate pin. The third transistor is a vertical JFET with a source node, a control node and a drain node. The source node of the third transistor electrically connects to a charge pin, and the control node of the third transistor to a charge-control pin. All of the drain nodes of the first, second and third transistors are electrically connected to a high-voltage pin.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: August 16, 2022
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Jhen Hong Li, Han Wei Chen
  • Patent number: 11417511
    Abstract: A method for drying a wafer at room temperature includes a cleaning step, a reacting step and a pressure releasing step. The cleaning step includes putting a processing workpiece into a cleaning solvent. The reacting step includes putting the processing workpiece along with the cleaning solvent into a reaction chamber, implanting a supercritical fluid into the reaction chamber, and increasing a pressure of the reaction chamber to dissolve the cleaning solvent in the supercritical fluid. A critical temperature of the supercritical fluid is below room temperature. The pressure releasing step includes releasing the pressure of the reaction chamber and discharging the supercritical fluid together with the cleaning solvent out of the reaction chamber, after completely dissolving the cleaning solvent in the supercritical fluid.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: August 16, 2022
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Chih-Cheng Yang, Wen-Chung Chen, Chuan-Wei Kuo, Pei-Yu Wu, Chun-Chu Lin