Abstract: A medical image analyzing system and a medical image analyzing method are provided and include inputting at least one patient image into a first model of a neural network module to obtain a result having determined positions and ranges of an organ and a tumor of the patient image; inputting the result into a second model of a first analysis module and a third model of a second analysis module, respectively, to obtain at least one first prediction value and at least one second prediction value corresponding to the patient image; and outputting a determined result based on the first prediction value and the second prediction value. Further, processes between the first model, the second model and the third model can be automated, thereby improving identification rate of pancreatic cancer.

Abstract: In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.

Abstract: A manufacturing method for a light-emitting device includes: forming a semiconductor stack; forming an electrode on the semiconductor stack, wherein the electrode includes a first top surface and a side surface; forming an insulating stack on the semiconductor stack and the electrode, wherein the insulating stack includes a plurality of first sub-layers with a first refractive index and a plurality of second sub-layers with a second refractive index alternately stacked; removing a portion of the insulating stack to expose the first top surface, leaving another portion of the insulating stack having a second top surface surrounding the first top surface, and a level of the second top surface is lower than or equal to that of the first upper surface; and forming an electrode pad on the insulating stack, wherein the electrode pad contacts the first top surface.

Abstract: A light-emitting device includes a semiconductor stack, an insulating reflective structure having an opening, and an electrode located on the insulating reflective structure and filled in the opening to electrically connect to the semiconductor stack. The semiconductor stack having includes a main surface, and a side surface inclined to the main surface. The light-emitting device has a dominant wavelength and a peak wavelength. The insulating reflective structure includes: a first part located on the main surface and having a first thickness; and a second part located on the side surface and having a second thickness different from the first thickness. The second part of the insulating reflective structure has a reflectivity of more than 90% for the dominant wavelength or the peak wavelength within an incident angle of 0° to 30°.

Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.

Abstract: A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.

Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; etching back the dummy gate layer; performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer, wherein a vertical thickness of the dummy gate layer is greater than a vertical thickness of the implantation region; forming a patterned hard mask stack over the implantation region; patterning the implantation region and the dummy gate layer by using the patterned hard mask stack as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

Abstract: A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

Abstract: Embodiments of the disclosure provide an angiography image determination method and an angiography image determination device. The method includes: obtaining a plurality of first images of a body part injected with a contrast medium; obtaining a plurality of corresponding second images by performing a first image preprocessing operation on each first image; obtaining a pixel statistical characteristic of each second image; finding a candidate image based on the pixel statistical characteristic of each second image; and finding a reference image corresponding to the candidate image among the plurality of first images.

Abstract: A chip-on-board module is provided. The chip-on-board module includes a chip and a substrate. The chip includes a plurality of chip contacts. The substrate includes a plurality of first leads and a plurality of second leads. The first leads and the second leads are coupled to a portion of the chip contacts. The first leads are arranged along a first axis. The second leads are arranged along a second axis. A first axis included angle is formed between the first axis and the second axis, and the first axis included angle is between 100° and 170°.

Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; and forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.

Abstract: Disclosed herein is a composition for modulating immunity, comprising Lactobacillus paracasei LT12, ?-glucan, and Bovine Colostrum Powder. Also provided is a method for modulating immunity, comprising administering to a subject in need a therapeutically effective amount of the composition, wherein the method is to enhance the expression of IL-6, IL-10, TNF-? and TGF-?1.

Abstract: Provided herein is a pharmaceutical composition comprising 1-2 part by weight of Schisandra chinensis powder and 5-10 part by weight of extract of Psidium guajava L. The composition can be used in the treatment of reducing blood uric acid, protecting pancreatic beta cell, and reducing body fat.

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

Abstract: The presented invention provides a data storage device. The memory device comprises an interface card and an expansion board. The interface card comprises a controller, a transmission interface, a plurality of first data storage elements and a first connector. The expansion board comprises a plurality of second data storage elements and a second connector. The expansion board is connected to the first connector of the interface card by the second connector to be stacked on the interface card. The controller is able to access data of the first data storage elements and the second data storage elements. Thus, the data storage capacity of the data storage device can be expanded by the expansion board, having the data storage elements, configured on the interface card.

Abstract: The present invention discloses a camera lens module. The present invention places and fixes an image sensor chip in an opening in a substrate and then assembles a frame, a lens holder and a lens, thereby minimizing the superposition height of the camera lens module and ensuring that the assembly is simpler and more effective.