Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer. The first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes a fluorine concentration that decreases from the inner surface and the outer surface towards a center of the first gate spacer. The structure further includes a second gate spacer disposed on the outer surface of the first gate spacer, and the second gate spacer includes a fluorine concentration that decreases from an outer surface towards an inner surface.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer and performing an oxide refill process to form a seamless dielectric material between the second and third semiconductor layers. The oxide refill process includes exposing the second and third semiconductor layers to a silicon-containing precursor at a first flow rate for a first duration to form a monolayer, and exposing the monolayer to an oxygen-containing precursor at a second flow rate for a second duration to form the seamless dielectric material, the second flow rate is about twice to about 20 times the first flow rate, and the second duration is about twice to about 20 times the first duration.

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: An aromatic liquid crystal polyester, having repeating units represented by formulae (1) and (2), respectively: where R?, Ar1, Ar2, Ar3, X, Y1, Y2 and Z are those as defined in the specification. Also, a liquid crystal polyester composition including the aromatic liquid crystal polyester and a solvent. The composition has an improved viscosity stability. Also, a liquid crystal polyester film prepared from the liquid crystal polyester composition and a method for manufacturing the same. The liquid crystal polyester film has excellent properties such as a low hygroscopicity and a low dissipation factor (Df).

Abstract: An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a transistor layer over a substrate and forming a trench in the transistor layer. A depth to width ratio of the trench is greater than or equal to 3. The method further includes filling the trench with a gap-fill material using a flowable chemical vapor deposition process, wherein a precursor and a reactant are used in the flowable chemical vapor deposition process, and a ratio of the precursor to the reactant is about 1.

Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.

Abstract: A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.

Abstract: A high thermal-stability separator and method for manufacturing thereof are disclosed. The high thermal-stability separator comprises a porous film and a titanium oxide or/and titanium hydroxide film, wherein the porous film comprises a porous substrate and a inorganic layer, wherein the inorganic layer comprises a plurality of inorganic particles and a binder, the inorganic layer is formed on at least one surface of the porous substrate, and the porous substrate and the inorganic layer have a plurality of interconnected porous structures; and the titanium oxide or/and titanium hydroxide film is formed on the surface and the inner walls of porous structures of the porous film. The present high thermal-stability separator can provide enhanced compression retention and excellent high temperature melt integrity, and maintain a satisfied air permeability (Gurley) after compression.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.

Abstract: A method is provided for forming a semiconductor device. A fin feature is formed on a semiconductor substrate, and a dummy gate feature is formed over the fin feature. The fin feature includes a sacrificial portion disposed over the semiconductor substrate, and a fin portion disposed over the sacrificial portion. The dummy gate feature is connected to the fin feature and the semiconductor substrate. Then, the sacrificial portion is removed to form a gap between the semiconductor substrate and the fin portion. A dielectric isolation layer is formed to fill the gap for electrically isolating the fin portion from the semiconductor substrate. Subsequently, source/drain features are formed over the dielectric isolation layer, and the dummy gate feature is processed to form a gate electrode feature on the fin portion.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

Abstract: The disclosure provides a method for manufacturing a separator, comprising the steps of: providing a nonporous precursor substrate; coating a heat-resistant slurry on a surface of the nonporous precursor substrate to form a heat-resistant coating layer, wherein the heat-resistant slurry comprises a binder and a plurality of inorganic particles; and stretching the nonporous precursor substrate with the heat-resistant coating layer formed thereon to generate a separator comprising a porous substrate and a heat-resistant layer; wherein the heat-resistant layer is disposed on the surface of the porous substrate in the range of 10% to 90% of the total surface area of the porous substrate.

Abstract: The disclosure provides a separator comprising a porous substrate and a heat-resistant layer disposed on a surface of the substrate. The heat-resistant layer comprises a binder and a plurality of inorganic particles, wherein the heat-resistant layer is disposed on the surface of the porous substrate in the range of 10% to 90% of the total surface area of the porous substrate.

Abstract: A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

Abstract: The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.

Abstract: The disclosure provides a method for manufacturing a separator, comprising the steps of: providing a nonporous precursor substrate; coating a heat-resistant slurry on a surface of the nonporous precursor substrate to form a heat-resistant coating layer, wherein the heat-resistant slurry comprises a binder and a plurality of inorganic particles; and stretching the nonporous precursor substrate with the heat-resistant coating layer formed thereon to generate a separator comprising a porous substrate and a heat-resistant layer; wherein the heat-resistant layer is disposed on the surface of the porous substrate in the range of 10% to 90% of the total surface area of the porous substrate.

Abstract: An all-MOSFET voltage reference circuit includes a first cascaded branch configured to generate a bias current and composed of a first current source and a diode-connected first N-type transistor connected at a first interconnected node; a second cascaded branch composed of a second current source, a diode-connected second N-type transistor and a third N-type transistor connected with the second N-type transistor disposed in between, wherein the second N-type transistor and the third N-type transistor are connected at a second interconnected node; a third cascaded branch composed of a third current source and a diode-connected fourth N-type transistor connected at an output node that provides a reference voltage; and an amplifier with a non-inverting node coupled to the first interconnected node and an inverting node coupled to the second interconnected node. A threshold voltage of the third N-type transistor is larger than a threshold voltage of the second N-type transistor.

Abstract: An aromatic liquid crystal polyester, having repeating units represented by formulae (1) and (2), respectively: where R?, Ar1, Ar2, Ar3, X, Y1, Y2 and Z are those as defined in the specification. Also, a liquid crystal polyester composition including the aromatic liquid crystal polyester and a solvent. The composition has an improved viscosity stability. Also, a liquid crystal polyester film prepared from the liquid crystal polyester composition and a method for manufacturing the same. The liquid crystal polyester film according to the present disclosure has excellent properties such as a low hygroscopicity and a low dissipation factor (Df).