Abstract: A first set of instructions associated with an egress of a datagram may be determined, the first set of instructions identifying a first subset of a second set of instructions, the first subset including multiple individual network identifiers identifying which network portion to transmit a replication of the datagram. Which one of the multiple individual network identifiers corresponds to the datagram may be determined from the first subset of the second set of instructions and may be based on the egress of the datagram, wherein each network identifier corresponds to a different egress. The replication of the datagram may be provided to the egress of the determined network identifier for transmission to the network portion as identified by the determined network identifier corresponding to the datagram.

Abstract: A network device for dynamically allocating memory locations to plurality of queues. The network device includes an assigning means for assigning a predefined amount of a temporary memory buffer and a shared memory buffer to each of a plurality of ports and for allocating a fixed allocation of the temporary memory buffer and the shared memory buffer to each of a plurality of queues associated with each port. After each queue has accumulated a predefined portion of data in the temporary memory buffer, the data is transmitted to the shared memory. The means for assigning reduces the shared memory access bandwidth by a predefined amount that is less than a processing bandwidth of a system clock.

Abstract: A network device for dynamically allocating memory locations to plurality of queues. The network device determines an amount of memory buffers that is associated with a port and assigns a fixed allocation of memory buffers to each of a plurality of queues associated with the port. The network device also shares remaining memory buffers among the plurality of queues, wherein the remaining memory buffers are used by at least one of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used by the queue. The network device further sets a limit threshold for each of the plurality of queues. The limit threshold determines how much of the remaining memory buffer may be used by each of the plurality of queues. When one of the limit threshold is reached for one of the plurality of queues or all of the remaining buffers are used, a request by the one of the plurality of queues is denied.

Abstract: A first set of instructions associated with an egress of a datagram may be determined, the first set of instructions identifying a first subset of a second set of instructions, the first subset including multiple individual network identifiers identifying which network portion to transmit a replication of the datagram. Which one of the multiple individual network identifiers corresponds to the datagram may be determined from the first subset of the second set of instructions and may be based on the egress of the datagram, wherein each network identifier corresponds to a different egress. The replication of the datagram may be provided to the egress of the determined network identifier for transmission to the network portion as identified by the determined network identifier corresponding to the datagram.

Abstract: A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the management unit to the external memory device. The command unit maintain at least one counter that is associated with current requests and compares the at least one counter to at least one predefined threshold in order to throttle the management unit when the at least one counter exceeds the at least one threshold. The network device further includes means for aligning information from the at least one external memory device with information transmitted from the command unit to the management unit and for ensuring that aligned information is accurate.

Abstract: A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the management unit to the external memory device. The command unit maintain at least one counter that is associated with current requests and compares the at least one counter to at least one predefined threshold in order to throttle the management unit when the at least one counter exceeds the at least one threshold. The network device further includes means for aligning information from the at least one external memory device with information transmitted from the command unit to the management unit and for ensuring that aligned information is accurate.

Abstract: A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the management unit to the external memory device. The command unit maintain at least one counter that is associated with current requests and compares the at least one counter to at least one predefined threshold in order to throttle the management unit when the at least one counter exceeds the at least one threshold. The network device further includes means for aligning information from the at least one external memory device with information transmitted from the command unit to the management unit and for ensuring that aligned information is accurate.

Abstract: A network device for dynamically allocating memory locations to plurality of queues. The network device includes an assigning means for assigning a predefined amount of a temporary memory buffer and a shared memory buffer to each of a plurality of ports and for allocating a fixed allocation of the temporary memory buffer and the shared memory buffer to each of a plurality of queues associated with each port. After each queue has accumulated a predefined portion of data in the temporary memory buffer, the data is transmitted to the shared memory. The means for assigning reduces the shared memory access bandwidth by a predefined amount that is less than a processing bandwidth of a system clock.

Abstract: A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the management unit to the external memory device. The command unit maintain at least one counter that is associated with current requests and compares the at least one counter to at least one predefined threshold in order to throttle the management unit when the at least one counter exceeds the at least one threshold. The network device further includes means for aligning information from the at least one external memory device with information transmitted from the command unit to the management unit and for ensuring that aligned information is accurate.

Abstract: A network device for dynamically allocating memory locations to plurality of queues. The network device includes means for determining an amount of memory buffers that is associated with a port and means for assigning a fixed allocation of memory buffers to each of a plurality of queues associated with the port. The network device also includes means for sharing remaining memory buffers among the plurality of queues, wherein the remaining memory buffers are used by at least one of the plurality of queues after the fixed allocation of memory buffers assigned to the queue is used by the queue. The network device further includes means for setting a limit threshold for each of the plurality of queues. The limit threshold determines how much of the remaining memory buffer may be used by each of the plurality of queues. When one of the limit threshold is reached for one of the plurality of queues or all of the remaining buffers are used, a request by the one of the plurality of queues is denied.

Abstract: The present invention discloses a regulator system (112) for regulating the output current and voltage (Vout) of a charge pump circuit (104). It is observed that the output current and voltage (Vout) of a charge pump circuit (104) can be regulated by varying the amplitude and frequency of a set of clock signals (modulated clocks). The present invention comprises means (decoders 1, 2; AM, FM units) for generating a set of control signals (VAD1-VFDn) as the function of the output current and voltage (Vout). The set of control signals (VAD1-VFDn) is coupled to a clock signal generation circuit (130) that generates a set of clock signals (modulated clocks) having a magnitude and a frequency depending on this set of at least one control signal. This set of clock signals (modulated clocks) is then used to drive the charge pump circuit (104). It is found that this regulator circuit (112) consumes less power than prior art regulator circuits.

Abstract: A user-programmable write protection scheme provides flexibility and superior write protect features for an integrated circuit memory which comprises an array of non-volatile erasable and programmable memory cells, including a plurality of sectors. Command logic detects command sequences indicating operations for the array, including a program operation, a sector erase operation, a read operation, a sector lock operation, and a sector unlock operation. The sector protect logic includes sector lock memory, including non-volatile memory cells that store sector lock signals for at least one sector in the array.

Abstract: An on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts) includes a sense circuit on the integrated circuit which generates an output indicating a level of the supply voltage. The on chip voltage supply circuit generates the on chip voltage in response to the output of the sense circuit and the supply voltage. The sense circuit output indicates the level of the supply voltage so that the on chip voltage supply circuit is able to adapt the amount of boosting utilized to produce the on chip voltage in response. The on chip voltage supply circuit generates the word line voltage at a node coupled to word line driving circuits in the device.

Abstract: The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input.

Abstract: A flash memory device includes a multiple checkpoint erase suspend algorithm. A user may issue an erase suspend command at anytime during an erase process. The erase procedure is suspended as fast as possible by allowing the erase procedure to be suspended at the first to occur of a plurality of checkpoints in the process. The block erase procedure includes a precondition phase (also called a pre-programming phase), in which a selected block is pre-programmed by applying a program potential, and then the pre-programming of the block is verified on a byte-by-byte basis. After the precondition phase, an erase phase is executed in which the selected block is erased by applying an erase potential to the block, and then verifying the erasing of the block. Erase suspend logic is coupled to the erase logic and executes an erase suspend procedure which interrupts the block erase procedure after receiving the erase suspend command during the first to occur of a set of checkpoints in the block erase procedure.

Abstract: Substantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence.