Patents by Inventor Wei-tsui Tseng

Wei-tsui Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect structures comprising capping layers with low dielectric constants and methods of making the same
    Patent number: 8026166
    Abstract: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 27, 2011
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Griselda Bonilla, Tien Cheng, Lawrence A. Clevenger, Stephan Grunow, Chao-Kun Hu, Roger A. Quon, Zhiguo Sun, Wei-tsui Tseng, Yiheng Xu, Yun Wang, Hyeok-sang Oh
  • INTERCONNECT STRUCTURES COMPRISING CAPPING LAYERS WITH LOW DIELECTRIC CONSTANTS AND METHODS OF MAKING THE SAME
    Publication number: 20100038793
    Abstract: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.
    Type: Application
    Filed: August 12, 2008
    Publication date: February 18, 2010
    Applicants: International Business Machines Corporation, Samsung Electronics Co., LTD, Chartered Semiconductor Manufacturing LTD.
    Inventors: Griselda Bonilla, Tien Cheng, Lawrence A. Clevenger, Stephan Grunow, Chao-Kun Hu, Roger A. Quon, Zhiguo Sun, Wei-tsui Tseng, Yiheng Xu, Yun Wang, Hyeok-Sang Oh