Abstract: The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist linewidth reduction for gate length definition followed by interconnect definition without patterned photoresist linewidth reduction. This has the advantages of an antireflective layer compatible with linewidth reduction and polysilicon etching.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: Pulsed plasma deposition of polymers as dielectrics for integrated circuit interconnects fills minimal gaps and yields a porous polymer with thermal stability by plasma off times sufficiently long to dissipate plasma on time energy input plus an anneal of the deposited polymer to drive off occluded monomers and small oligomers.

Abstract: An integrated circuit structure (8) includes a plurality of solid state electronic devices and a plurality of conductive elements (12, 14) that electrically couple the electronic devices. The integrated circuit structure (8) also includes a dielectric layer (16) positioned between two or more of the conductive elements (12, 14). A liner (18) is positioned between at least a portion of the dielectric layer (16) and a conductive element (12, 14). The liner (18) is formed from a compound that includes silicon and either carbon and nitrogen.

Abstract: A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

Abstract: A system and method for evacuating potential wafer-corroding and contaminating residual process gases from the interior of a semiconductor wafer pod before, after or both before and after a process is performed on the wafers. The residual process gases are first evacuated from the wafer pod, which is next charged with a fresh supply of inert gas. The system is adapted to evacuate and charge the wafer pod as the wafer pod typically rests on a load port of a SMIF prior to transfer of the pod to another destination in the semiconductor fabrication facility, prior to internalization of the wafers into a processing tool, or both.

Abstract: A system and method for evacuating potential wafer-corroding and contaminating residual process gases from the interior of a semiconductor wafer pod before, after or both before and after a process is performed on the wafers. The residual process gases are first evacuated from the wafer pod, which is next charged with a fresh supply of inert gas. The system is adapted to evacuate and charge the wafer pod as the wafer pod typically rests on a load port of a SMIF prior to transfer of the pod to another destination in the semiconductor fabrication facility, prior to internalization of the wafers into a processing tool, or both.

Abstract: An accelerated thermal stress cycle test which can be conducted in a significantly reduced test time compared to the conventional test is provided. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350° C. in an inert gas in about 2 min., and then cooled down to not higher than 70° C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.

Abstract: A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).

Abstract: An IC includes one or more gaps (18) substantially filled with silicon dioxide (30). The silicon dioxide (30) is deposited into the gaps (18) in response to the reaction of hexamethyldisiloxane (HMDSO) (26) with ozone (28) during a plasma-enhanced CVD (PECVD) process. The IC may be fabricated by inserting a substrate into a chamber. HMDSO (26) and ozone (28) are introduced into the chamber. The HMDSO (26) reacts with the ozone (28) to produce silicon dioxide (30), which is then deposited on the surface (10) of the substrate.

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewall bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: An integrated circuit structure (8) includes a plurality of solid state electronic devices and a plurality of conductive elements (12, 14) that electrically couple the electronic devices. The integrated circuit structure (8) also includes a dielectric layer (16) positioned between two or more of the conductive elements (12, 14). A liner (18) is positioned between at least a portion of the dielectric layer (16) and a conductive element (12, 14). The liner (18) is formed from a compound that includes silicon and either carbon and nitrogen.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewalk bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewalk bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewall bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: Pulsed plasma deposition of polymers as dielectrics for integrated circuit interconnects fills minimal gaps and yields a porous polymer with thermal stability by plasma off times sufficiently long to dissipate plasma on time energy input plus an anneal of the deposited polymer to drive off occluded monomers and small oligomers.

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).