Patents by Inventor Wei Xin

Wei Xin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250024483
    Abstract: A method and apparatus for reducing inter-cell interference are provided. The method includes: selecting, in a cell, multiple radio frequency units within a predetermined range of a location of a User Equipment (UE); and sending service channel data only on the multiple radio frequency units when scheduling the UE. By means of the embodiments of the present disclosure, data is sent only to radio frequency units which are located near a user and selected according to a location of the user in a cell, and data is not sent to other radio frequency units in the cell, so that inter-cell interference may be reduced.
    Type: Application
    Filed: October 18, 2022
    Publication date: January 16, 2025
    Inventors: Guohui LONG, Wei TENG, Qin XIN
  • Publication number: 20250008842
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Application
    Filed: September 15, 2024
    Publication date: January 2, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Publication number: 20240420901
    Abstract: A pressure module comprises a substrate, a support structure and a pressing membrane. The support structure is connected to the substrate and the pressing membrane to form an accommodating cavity between the substrate and the pressing membrane. An electrode is disposed on a surface of the substrate or the pressing membrane and a variable resistance layer is respectively disposed on the opposite surface of the other of the substrate and the pressing membrane. On application of pressure to the pressing membrane, the pressing membrane is elastically deformed and the variable resistance layer is brought into contact with the electrode to form a contact area and a resistance value between the variable resistance layer and the electrode. The contact area and the elastic deformation is positively correlated.
    Type: Application
    Filed: October 19, 2022
    Publication date: December 19, 2024
    Inventors: Zhang WEN, Xu FENG, Wei XIN, Cao JIN, You DAWEI, Lv BING, Li ZEFENG, Wang SHICHAO
  • Publication number: 20240371579
    Abstract: A button structure comprises a keycap, an elastic body, a scissor mechanism, and a piezoresistive film sensor arranged on a support plate. The scissor mechanism and the elastic body are arranged between the keycap and the piezoresistive film sensor. The piezoresistive film sensor comprises a first pressure sensing area and a second pressure sensing area. The elastic body corresponds to the first pressure sensing area and the scissor mechanism corresponds to the second pressure sensing area, such that, when a pressure is applied to the keycap, a first pressure acts on the elastic body to generate pressure on the first pressure sensing area and a second pressure acts on the scissor mechanism to generate pressure on the second pressure sensing area.
    Type: Application
    Filed: August 25, 2021
    Publication date: November 7, 2024
    Inventors: Zhang WEN, Xu FENG, Wei XIN, Cao JIN, You DAWEI, Lv BING, Li ZEFENG, Wang SHICHAO
  • Patent number: 12120962
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: October 15, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Patent number: 12097692
    Abstract: An apparatus for use in the assembly of an electronic device, such as a mobile telephone, comprises a pressure sensor. The pressure sensor is embedded within an inner elastic layer and the inner elastic layer is embedded within an outer elastic layer. The inner elastic layer has an elastic modulus which is greater than the elastic modulus of the outer elastic layer.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: September 24, 2024
    Assignee: Peratch Holdco Limited
    Inventors: Xu Feng, Cao Jin, Sun Kun, Wei Xin
  • Publication number: 20240168835
    Abstract: A hard disk failure prediction method, a hard disk failure prediction system, a device and a medium are provided. The method includes: acquiring SMART attribute values of a hard disk; performing data standardization processing on the SMART attribute values, and filtering the processed SMART attribute values to obtain filtered SMART attribute values; constructing a hard disk failure prediction key database according to the filtered SMART attribute values, a warning value and a rating value corresponding to the filtered SMART attribute values; optimizing a decision tree-based hard disk failure prediction model by using the hard disk failure prediction key database to obtain an optimized decision tree-based hard disk failure prediction model; and acquiring SMART attribute values of a target hard disk hard disk, and predicting a health of the target hard disk to obtain a prediction result. The present disclosure improves the accuracy of failure prediction.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 23, 2024
    Inventors: Yujiang Wang, Shicheng Wei, Yi Liang, Bo Wang, Wei Xin, Fangjie Lu, Chao Zheng
  • Publication number: 20240170299
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Inventors: KUN-JU LI, ANG CHAN, HSIN-JUNG LIU, WEI-XIN GAO, JHIH-YUAN CHEN, CHUN-HAN CHEN, ZONG-SIAN WU, CHAU-CHUNG HOU, I-MING LAI, FU-SHOU TSAI
  • Publication number: 20240081154
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Patent number: 11923205
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
  • Publication number: 20240071988
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.
    Type: Application
    Filed: October 11, 2022
    Publication date: February 29, 2024
    Inventors: Kun-Ju LI, Hsin-Jung LIU, Wei-Xin GAO, Jhih-Yuan CHEN, Ang CHAN, Chau-Chung HOU
  • Publication number: 20240055401
    Abstract: A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.
    Type: Application
    Filed: September 8, 2022
    Publication date: February 15, 2024
    Inventors: Kun-Ju LI, Hsin-Jung LIU, Zong-Sian WU, Wei-Xin GAO, Jhih-Yuan CHEN, Ang CHAN, Chau-Chung HOU, Hsiang-Chi CHIEN, I-Ming LAI
  • Publication number: 20240013990
    Abstract: A key mechanism comprises an elastic structure comprising a first cavity located above a second cavity which are spaced apart from each other. The key mechanism comprises first and second button structures. The second button structure comprises an electrode layer on an upper wall of the second cavity and an electrode layer on a lower wall of the second cavity. The second button structure has an elastic body on the surface of one of the electrode layers. The first button structure is configured to generate a first key signal when a force is applied to an upper wall of the first cavity and compress the upper wall of the second cavity upon application of that force. The electrode layers come into contact to generate a second key signal in response to elastic deformation of the elastic body when the force is applied.
    Type: Application
    Filed: June 11, 2021
    Publication date: January 11, 2024
    Inventors: Xu Feng, Cao JIN, Sun Kun, Wei Xin
  • Patent number: 11868554
    Abstract: A pressure sensor comprises a first sensing module comprising a first negative electrode and first support structures arranged at intervals on the first negative electrode. A first flexible insulating layer covers an upper surface of the first support structures and first positive electrodes are arranged at intervals on a lower surface of the first flexible insulating layer and distributed between the first support structures. A second sensing module comprises a second negative electrode disposed on the first flexible insulating layer and second support structures are arranged at intervals on the second negative electrode. A second flexible insulating layer covers an upper surface of the second support structures. Second positive electrodes are arranged on a lower surface of the second flexible insulating layer at intervals and distributed between the second support structures. The first support structures are offset from the second support structures.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 9, 2024
    Assignee: Peratech Holdco Limited
    Inventors: Xu Feng, Cao Jin, Sun Kun, Wei Xin
  • Patent number: 11871677
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Publication number: 20230403946
    Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Laio, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20230354715
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Application
    Filed: June 27, 2023
    Publication date: November 2, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20230341939
    Abstract: A touch device comprises a base, a membrane pressure sensor arranged on the base, a touch sensing layer covering the membrane pressure sensor, and a force feedback structure arranged on the lower surface of the touch sensing layer and electrically connected to the membrane pressure sensor. The membrane pressure sensor is configured to generate a pressing signal related to the force applied to it, and the force feedback structure is configured to receive the pressing signal and generate a feedback force corresponding to it.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 26, 2023
    Inventors: Cao JIN, Xu FENG, Wei XIN, Lv BING
  • Publication number: 20230320229
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: May 10, 2023
    Publication date: October 5, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11778922
    Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang