Abstract: This application discloses an LDPC encoding and decoding method and a related apparatus. This application supports 802.11 series protocols such as Wi-Fi 8, UWB. The method includes: performing low-density parity-check LDPC encoding on an information bit sequence based on a parity check matrix, to obtain a first code word, where the parity check matrix complies with a base matrix, and the base matrix meets one of the following: Each row in the first two columns of the base matrix includes at least one 1, or the first two columns of the base matrix include “1 0” and “0 1” that alternate regularly, and “1 1” is included between “1 0” and “0 1”; and sending the first code word. The parity check matrix complies with the base matrix, which can accelerate an overall decoding convergence speed of a system.

Abstract: The disclosure provides a security analysis method and system based on protocol state, which relates to the technical field of protocol security protection. The method includes the following: a node traversal table is built, the node traversal table is scanned and analyzed according to the protocol trigger sequence rule, a first security evaluation factor of a protocol stack is determined, and a second security evaluation factor of each protocol is determined based on protocol normal application rule, and the trustworthiness degree of the second security factor is determined based on the first security factor, and the second security factor is revised based on the trustworthiness degree, and the security state of the protocol is determined according to the revised second security factor, thus the analysis of the protocol state is realized, and the security of the protocol can be accurately determined.

Abstract: The disclosure provides a security analysis method and system based on protocol state, which relates to the technical field of protocol security protection. The method includes the following: a node traversal table is built, the node traversal table is scanned and analyzed according to the protocol trigger sequence rule, a first security evaluation factor of a protocol stack is determined, and a second security evaluation factor of each protocol is determined based on protocol normal application rule, and the trustworthiness degree of the second security factor is determined based on the first security factor, and the second security factor is revised based on the trustworthiness degree, and the security state of the protocol is determined according to the revised second security factor, thus the analysis of the protocol state is realized, and the security of the protocol can be accurately determined.

Abstract: A display panel is provided, which includes a first substrate and a second substrate arranged opposite to each other. The first substrate includes a first electrode and a second electrode. The second substrate includes a light shielding layer. The light shielding layer includes a light transmitting region and a light shielding region. The first electrode includes slits extending in a first direction, and an orthographic projection of two ends of at least one of the slits onto the first substrate is within an orthographic projection of the light shielding region onto the first substrate. A display panel and a display device are also provided.

Abstract: This application provides an LDPC code encoding method and a communication apparatus, to meet a requirement of increasing redundant bits through retransmission in an IR-HARQ mechanism, so as to decrease a channel coding rate, and improve decoding performance of an LDPC code. In the method, a check matrix of the LDPC code is used as a basic matrix, and the basic matrix is extended to obtain a mother matrix compatible with a plurality of code rates. During LDPC encoding, a transmit device reads, from the mother matrix, a check matrix corresponding to a required code rate, and performs LDPC encoding on an information bit sequence based on the read check matrix. LDPC encoding is performed on the information bit sequence by using check matrices of different sizes, to obtain different quantities of redundant bits.

Abstract: A method and apparatus for reducing inter-cell interference are provided. The method includes: selecting, in a cell, multiple radio frequency units within a predetermined range of a location of a User Equipment (UE); and sending service channel data only on the multiple radio frequency units when scheduling the UE. By means of the embodiments of the present disclosure, data is sent only to radio frequency units which are located near a user and selected according to a location of the user in a cell, and data is not sent to other radio frequency units in the cell, so that inter-cell interference may be reduced.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: A pressure module comprises a substrate, a support structure and a pressing membrane. The support structure is connected to the substrate and the pressing membrane to form an accommodating cavity between the substrate and the pressing membrane. An electrode is disposed on a surface of the substrate or the pressing membrane and a variable resistance layer is respectively disposed on the opposite surface of the other of the substrate and the pressing membrane. On application of pressure to the pressing membrane, the pressing membrane is elastically deformed and the variable resistance layer is brought into contact with the electrode to form a contact area and a resistance value between the variable resistance layer and the electrode. The contact area and the elastic deformation is positively correlated.

Abstract: A button structure comprises a keycap, an elastic body, a scissor mechanism, and a piezoresistive film sensor arranged on a support plate. The scissor mechanism and the elastic body are arranged between the keycap and the piezoresistive film sensor. The piezoresistive film sensor comprises a first pressure sensing area and a second pressure sensing area. The elastic body corresponds to the first pressure sensing area and the scissor mechanism corresponds to the second pressure sensing area, such that, when a pressure is applied to the keycap, a first pressure acts on the elastic body to generate pressure on the first pressure sensing area and a second pressure acts on the scissor mechanism to generate pressure on the second pressure sensing area.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: An apparatus for use in the assembly of an electronic device, such as a mobile telephone, comprises a pressure sensor. The pressure sensor is embedded within an inner elastic layer and the inner elastic layer is embedded within an outer elastic layer. The inner elastic layer has an elastic modulus which is greater than the elastic modulus of the outer elastic layer.

Abstract: A hard disk failure prediction method, a hard disk failure prediction system, a device and a medium are provided. The method includes: acquiring SMART attribute values of a hard disk; performing data standardization processing on the SMART attribute values, and filtering the processed SMART attribute values to obtain filtered SMART attribute values; constructing a hard disk failure prediction key database according to the filtered SMART attribute values, a warning value and a rating value corresponding to the filtered SMART attribute values; optimizing a decision tree-based hard disk failure prediction model by using the hard disk failure prediction key database to obtain an optimized decision tree-based hard disk failure prediction model; and acquiring SMART attribute values of a target hard disk hard disk, and predicting a health of the target hard disk to obtain a prediction result. The present disclosure improves the accuracy of failure prediction.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.

Abstract: A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.

Abstract: A key mechanism comprises an elastic structure comprising a first cavity located above a second cavity which are spaced apart from each other. The key mechanism comprises first and second button structures. The second button structure comprises an electrode layer on an upper wall of the second cavity and an electrode layer on a lower wall of the second cavity. The second button structure has an elastic body on the surface of one of the electrode layers. The first button structure is configured to generate a first key signal when a force is applied to an upper wall of the first cavity and compress the upper wall of the second cavity upon application of that force. The electrode layers come into contact to generate a second key signal in response to elastic deformation of the elastic body when the force is applied.

Abstract: A pressure sensor comprises a first sensing module comprising a first negative electrode and first support structures arranged at intervals on the first negative electrode. A first flexible insulating layer covers an upper surface of the first support structures and first positive electrodes are arranged at intervals on a lower surface of the first flexible insulating layer and distributed between the first support structures. A second sensing module comprises a second negative electrode disposed on the first flexible insulating layer and second support structures are arranged at intervals on the second negative electrode. A second flexible insulating layer covers an upper surface of the second support structures. Second positive electrodes are arranged on a lower surface of the second flexible insulating layer at intervals and distributed between the second support structures. The first support structures are offset from the second support structures.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.