Abstract: The present invention provides a material-based subdomain hybrid cellular automata algorithm for solving material optimization of thin-walled frame structures, including an outer loop and an inner loop: the outer loop is to define and update the target cost for the inner loop; the inner loop is to adjust material using a PID control strategy according to the nominal flow stress of a current cell and the nominal flow stress of candidate materials, so that a current cost of the inner loop converges to the target cost.

Abstract: A method comprising receiving, from a first infrared image capture device, three images including gas equipment including a first image captured at a first time period, a second image captured at a second time period, and a third image captured at a third time period, the three images capturing an infrared spectrum, interpreting one of the three images in a red color channel of an RGB image where pixels are red-tonal in coloring, interpreting an other of the three images in a green color channel of the RGB image where pixels are green-tonal in coloring, interpreting a remaining of the three images in a blue color channel of the RGB image where pixels are blue-tonal in coloring, and providing the RGB image for display, the RGB image indicating movement as at least one color that is different from color of at least some of the gas equipment.

Abstract: A system configured to receive video and/or images from an image capture device over a livestock path, generate feature maps from an image of the video by applying at least a first convolutional neural network, slide a window across the feature maps to obtain a plurality of anchor shapes, determine if each anchor shape contains an object to generate a plurality of regions of interest, each of the plurality of regions of interest being a non-rectangular, polygonal shape, extract feature maps from each region of interest, classify objects in each region of interest, in parallel with classification, predict segmentation masks on at least a subset of the regions of interest in a pixel-to-pixel manner, identify individual animals within the objects based on classifications and the segmentation masks, and count individual animals based on identification, and provide the count to a digital device for display, processing, and/or reporting.

Abstract: The present application discloses a method, system, and computer system for predicting responses to DNS queries. The method includes receiving a DNS query comprising a subdomain portion and a root domain portion from a client device, determining whether to obtain target address information corresponding to the DNS from a predictive cache, in response to determining to obtain the target address information from the predictive cache, obtaining the target address information from the predictive cache, and providing the target address information to the client device.

Abstract: A catalyst system is disclosed. The catalyst system may include a pre-catalyst and a co-catalyst. The pre-catalyst includes one or more chromium compounds coordinated with a ligand. The co-catalyst includes one or more organoaluminum compounds, wherein: the ligand has a structure according to formula (I): In formula (I), R1, R2, R3, and R4 are independently chosen from (C6-C60) aryl, optionally substituted with one or more RS, wherein RS is a (C1-C50) hydrocarbyl or a (C1-C50) heterohydrocarbyl. In formula (I), R5 is a (C9-C60) aryl or a (C4-C60) heteroaryl, optionally substituted with one or more RS, wherein RS is a (C1-C50) hydrocarbyl or a (C1-C50) heterohydrocarbyl, provided that R5 is not naphthyl or triptycenyl.

Abstract: A semiconductor device includes Number of decks that are stacked up in a Z direction and extend in parallel with an X-Y plane. N is an integer greater than 1. Each deck includes alternating word line layers and insulating layers. The N number of decks includes a first deck and a second deck adjacent to the first deck. A multi-deck gate line slit (GLS) structure extends in an X-Z plane and cuts through the word line layers and the insulating layers of the N number of decks. The multi-deck GLS structure has a first sidewall in the first deck, a second sidewall in the second deck, and a third sidewall at a border between the first deck and the second deck. The third sidewall connects the first sidewall and the second sidewall.

Abstract: A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.

Abstract: A semiconductor device includes N number of decks. Each deck includes alternating word line layers and insulating layers. Each deck includes two first gate line slit (GLS) structures and a second GLS structure positioned between the two first GLS structures. The two first GLS structures and the second GLS structures each extend in an X-Z plane and cut through the word line layers and the insulating layers of the respective deck. At least one second GLS structure of at least one deck in the N umber of decks includes multiple sub-GLS structures. The multiple sub-GLS structures are separate from each other.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device can include a trench formed in a first dielectric layer, a trench filler layer that fills a portion of the trench, a conductive layer over the trench filler layer, and a second dielectric layer over the conductive layer. The second dielectric layer is disposed in the trench. The semiconductor device can also include a contact structure configured to connect to the conductive layer through a hole in the second dielectric layer.

Abstract: The present invention relates to increasing longevity of the nitrogen content of soil through improved liquid delivery formulations of nitrification inhibitors. The liquid formulation can also be comprised of nitrification inhibitors and optionally urease inhibitors that are blended solutions of each. The nitrification inhibitors are present in a mixture that comprises both a protic and an aprotic solvent system. The novel formulations are designed to be applied to fertilizers, especially urea and manure based fertilizers. The delivery formulations provide an environmentally sound and inherently safe solvating system that improves the storage stability of the urease inhibitors by utilizing liquid organic non-water containing solvents, maintains the nitrification inhibitors in solution to storage temperatures of at least 10° C., and provides improved application to fertilizer of nitrification inhibitors.

Abstract: The present disclosure relates to an electronic device, a wireless communication method, and a computer-readable medium. The electronic device for wireless communication according to one embodiment comprises a processing circuit. The processing circuit is configured to obtain a set of collaborative devices of a target device, the set of collaborative devices comprising one or more collaborative devices. The processing circuit is further configured to control to send data for the target device to the target device and at least one collaborative device so that the at least one collaborative device forwards the data to the target device.

Abstract: Provided is a method for producing washing enzyme having protease resistance. According to the method, the washing enzyme having resistance to protease is obtained by carrying out fusion expression on a gene of the washing enzyme with the gene of a protease inhibitory peptide, thereby facilitating maintaining the stability of various enzyme components in an enzyme-containing detergent, and improving the use effect of the detergent.

Abstract: The present invention relates to increasing longevity of the nitrogen content of soil through improved liquid delivery formulations of nitrification inhibitors. The liquid formulation can also be comprised of nitrification inhibitors and optionally urease inhibitors that are blended solutions of each. The nitrification inhibitors are present in a mixture that comprises both a protic and an aprotic solvent system. The novel formulations are designed to be applied to fertilizers, especially urea and manure based fertilizers. The delivery formulations provide an environmentally sound and inherently safe solvating system that improves the storage stability of the urease inhibitors by utilizing liquid organic non-water containing solvents, maintains the nitrification inhibitors in solution to storage temperatures of at least 10° C., and provides improved application to fertilizer of nitrification inhibitors.

Abstract: A soft start circuit of a UPS relay includes a three-phase pre-charging module, a first PFC module, a second PFC module, a relay module, a three-phase input voltage detection module, a bus voltage detection module and a relay control module. The relay control module is electrically connected to the three-phase input voltage detection module and the bus voltage detection module and controls the connection of the relay module, to control part of relays in the relay module to be turned on based on the A-phase input voltage, the B-phase input voltage, the C-phase input voltage and the bus voltage to soft start the relay. The relay can be safely turned on without being damaged by an impact current in a case that an input voltage is unbalanced.

Abstract: A semiconductor device includes a base and a stack structure. The base includes a first surface defining at least one memory plane region. The stack structure is disposed on the first surface, and includes a first portion located at the edge of the memory plane region and a second portion different from the first portion. The first portion includes first contact structures penetrating through the stack structure in a first direction and extending to the base. The second portion includes second contact structures electrically connected with corresponding gate conductor layers in the stack structure. A top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.

Abstract: A semiconductor structure includes a stack structure, first gate isolation structures, and conductive structures. The stack structure includes gate layers and first dielectric layers disposed alternately. The first gate isolation structures extend along a first direction, and the first gate isolation structures are arranged at intervals along a second direction and divide the stack structure into at least one block comprising a memory region and a connection region that are distributed along the first direction. The conductive structures are located in the connection region, and orthographic projections of upper ends of at least two conductive structures on a reference plane at least partially overlap. The reference plane is perpendicular to the second direction, and the first direction is perpendicular to the second direction.

Abstract: Disclosed is a control circuit for a relay in an uninterruptible power supply, comprising a plurality of capacitors comprising at least a first capacitor; and a plurality of relays comprising at least a first relay, a second relay, a third relay and a fourth relay, wherein a first terminal of the first relay is connected to a positive electrode of a battery, a second terminal of the first relay is connected to a first terminal of the first capacitor, a first terminal of the second relay is connected to a negative electrode of the battery, a second terminal of the second relay is connected to a second terminal of the first capacitor, a second terminal of the third relay is connected to the second terminal of the first relay, and a second terminal of the fourth relay is connected to the second terminal of the second relay.

Abstract: A semiconductor device and a manufacturing method thereof, a memory and a memory system are disclosed. The method includes: providing a substrate and stacked layers on the substrate, the stacked layers comprising interlayer sacrificial layers and interlayer insulating layers which are alternately stacked; removing part of the interlayer sacrificial layer to form a gate gap; sequentially forming a protection layer and a gate structure in the gate gap; forming a contact hole extending from a side of the stacked layers facing away from the substrate into a remaining interlayer sacrificial layer and exposing the protection layer; removing the protection layer exposed in the contact hole to expose the gate structure; forming a contact structure in the contact hole in such a way that the contact structure is connected with the gate structure.

Abstract: Credential phishing attack mitigation is disclosed. A URL that is associated with a suspected credential phishing web page is received. The suspected credential phishing web page is one that includes at least one element soliciting at least one credential. The URL is included in a message having at least one intended recipient. An artificial credential is provided to the suspected credential phishing web page. An indication is received that, subsequent to providing the artificial credential to the suspected credential phishing web page, an attempted use of the artificial credential to access a resource was made. In response to receiving the indication that the attempted use of the artificial credential to access the resource has been made, at least one remedial action is taken with respect to the suspected credential phishing web page.