Patents by Inventor Weiyang Jiang

Weiyang Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Universal cell model for array and circuit simulation using the same
    Patent number: 10169524
    Abstract: In some embodiments, in a method, for each array of at least a first array, a layout of the first array which comprises a plurality of cells, and a plurality of first circuit paths running across at least one side length in an array size configuration of the first array is received. Each of the plurality of cells is configured with a first node that is coupled to a respective one of the plurality of first circuit paths. A first representative characteristic associated with the plurality of first circuit paths is extracted. A universal cell model applied to each cell in a second array is generated based on a base cell model comprising parameters independent of positions in the second array, and the first representative characteristic.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Lin Sun, Tingting Lu, Weiyang Jiang, Feng Zhu, Zhi Zhong Hu, Mu-Jen Huang
  • Word line driving unit with a boost voltage generator and memory device including the same
    Patent number: 10090032
    Abstract: A method includes delaying an input voltage signal to generate an output voltage, enabling a capacitor unit to apply across a word line driver a boosted voltage greater than the output voltage, and enabling the word line driver to provide a driving voltage that corresponds to the boosted voltage. A word line driving unit that performs the method and a memory device that includes the word line driving unit are also disclosed.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-En Bu, Ching-Wei Wu, He-Zhou Wan, Weiyang Jiang
  • Word Line Driving Unit With a Boost Voltage Generator and Memory Device Including the Same
    Publication number: 20170345473
    Abstract: A method includes delaying an input voltage signal to generate an output voltage, enabling a capacitor unit to apply across a word line driver a boosted voltage greater than the output voltage, and enabling the word line driver to provide a driving voltage that corresponds to the boosted voltage. A word line driving unit that performs the method and a memory device that includes the word line driving unit are also disclosed.
    Type: Application
    Filed: February 7, 2017
    Publication date: November 30, 2017
    Inventors: Ming-En Bu, Ching-Wei Wu, He-Zhou Wan, Weiyang Jiang
  • UNIVERSAL CELL MODEL FOR ARRAY AND CIRCUIT SIMULATION USING THE SAME
    Publication number: 20160292347
    Abstract: In some embodiments, in a method, for each array of at least a first array, a layout of the first array which comprises a plurality of cells, and a plurality of first circuit paths running across at least one side length in an array size configuration of the first array is received. Each of the plurality of cells is configured with a first node that is coupled to a respective one of the plurality of first circuit paths. A first representative characteristic associated with the plurality of first circuit paths is extracted. A universal cell model applied to each cell in a second array is generated based on a base cell model comprising parameters independent of positions in the second array, and the first representative characteristic.
    Type: Application
    Filed: March 7, 2016
    Publication date: October 6, 2016
    Inventors: LIN SUN, TINGTING LU, WEIYANG JIANG, FENG ZHU, ZHI ZHONG HU, MU-JEN HUANG
  • Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof
    Patent number: 8305791
    Abstract: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wei Wu, Cheng Hung Lee, Li-Chen Chen, Weiyang Jiang
  • MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF
    Publication number: 20110019460
    Abstract: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.
    Type: Application
    Filed: May 20, 2010
    Publication date: January 27, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Wei Wu, Cheng Hung Lee, Li-Chen Chen, Weiyang Jiang