Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, and forming a gate structure to wrap around each of the nanostructures.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.

Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surfac

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure, and a source/drain structure in the fin structure and adjacent to the gate structure. The source/drain structure includes: a first epitaxial layer over the fin structure, a second epitaxial layer over the first epitaxial layer, and an epitaxial capping layer over the second epitaxial layer. The semiconductor structure also includes a silicide layer formed in contact with the source/drain structure. The silicide layer has a curved bottom surface, and the curved bottom surface of the silicide layer intersects with the second epitaxial layer and the epitaxial capping layer.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an inner spacer layer between two adjacent nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the inner spacer layer, and a barrier layer adjacent to the inner spacer layer. The barrier layer extends from the first position to the second position, and the first position is between the inner spacer layer and the nanostructure, and the second position is between the nanostructures and the S/D structure.

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

Abstract: An integrated circuit (IC) structure includes a gate structure, source/drain epitaxial structures, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source/drain epitaxial structures are respectively on opposite sides of the gate structure. The front-side interconnection structure is on front-sides of the source/drain epitaxial structures. The backside dielectric layer is on backsides of the source/drain epitaxial structures. The backside via extends through the backside dielectric layer to one of the source/drain epitaxial structures, and has a maximal lateral dimension larger than a lateral dimension of the source/drain epitaxial structure.

Abstract: A semiconductor device includes a first channel region above a substrate, a first metal gate structure engaging the first channel region, a first gate sidewall spacer disposed on sidewalls of the first metal gate structure, a second channel region above the substrate, a second metal gate structure engaging the second channel region, a second gate sidewall spacer disposed on sidewalls of the second metal gate structure, a first interposing feature disposed adjacent to the first channel region, a first epitaxial feature disposed on the first interposing feature and abutting the first channel region, a second interposing feature disposed adjacent to the second channel region, and a second epitaxial feature disposed on the second interposing feature and abutting the second channel region. A bottom surface of the second epitaxial feature is above a bottom surface of the first epitaxial feature.

Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

Abstract: A semiconductor structure includes a channel region over a substrate, a gate structure engaging the channel region, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the channel region, an S/D contact landing on a top surface of the S/D feature, and a dielectric layer disposed on a sidewall of the gate spacer. The S/D feature includes a first layer and a second layer underneath the first layer. The second layer differs from the first layer in composition. The dielectric layer interfaces with both the first layer and the second layer of the S/D feature. In a cross-sectional view along a lengthwise direction of the channel region, a bottommost point of the top surface of the S/D feature is below a top surface of the channel region.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: Methods and associated devices including the fabrication of a semiconductor structure that provides a silicon-on-insulator substrate. The semiconductor structure may be formed by providing a base substrate, forming a sacrificial layer over the base structure, and forming a semiconductor layer over the sacrificial layer. The sacrificial layer is removed to form a void that is filled with oxide. The semiconductor structure includes a dielectric support feature extending through the semiconductor and oxide layers and/or a portion of the oxide layer extends to the surface of the semiconductor layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first and second semiconductor layers are alternately stacked over a substrate, is formed, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers are laterally etched in the source/drain space, a first insulating layer is formed on a sidewall of the source/drain space, the first insulating layer is partially etched, thereby forming a first bottom spacer at a bottom of the source/drain space, a second insulating layer is formed on the sidewall of the source/drain space, the second insulating layer is partially etched, thereby forming inner spacers on end faces of the first semiconductor layers and leaving a part of the second insulating layer as a second bottom spacer at the bottom of the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space.

Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

Abstract: Multi-gate transistor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a fin-shaped structure over a substrate and including channel layers interleaved by sacrificial layers, recessing the fin-shaped structure to form a source/drain recess, recessing the sidewalls of the sacrificial layers to form inner spacer recesses, depositing a dielectric layer over the substrate and the inner spacer recesses, depositing a polymer layer over the dielectric layer, etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the portion of the substrate, and epitaxially depositing more than one epitaxial layer from the sidewalls of the plurality of channel layers to form a source/drain feature in the source/drain recess. The source/drain feature and the inner spacer layer define a gap.

Abstract: A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a PAI process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers.

Abstract: A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.

Abstract: A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.