Patents by Inventor Wei-Yang Lee

Wei-Yang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290861
    Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230253450
    Abstract: A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20230253260
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 10, 2023
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20230253478
    Abstract: A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 10, 2023
    Inventors: I-Hsieh WONG, Wei-Yang LEE, Yen-Ming CHEN, Feng-Cheng YANG
  • Publication number: 20230253474
    Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 10, 2023
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230246091
    Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Inventors: Wei-Yang Lee, Chih-Shan Chen
  • Publication number: 20230231320
    Abstract: An array antenna includes a flexible substrate formed by stacked liquid crystal polymer (LCP) layers and has at least one feed point. At least one serial antenna is arranged on the flexible substrate, and a microstrip is extended from the feed point to connect a plurality of radiating elements in series to form the serial antenna. The tail end one of the radiating elements of the serial antenna is connected to one end of a ground microstrip, and another end of the ground microstrip is short-circuited to the ground. The length of the ground microstrip is approximately one fourth of the wavelength of the center frequency of the array antenna. Feeding sections where microstrips feeding to the radiating elements are in a horn and/or groove shape. Desired frequency and bandwidth may be obtained by adjusting lengths and widths of feeding sections respectively.
    Type: Application
    Filed: October 24, 2022
    Publication date: July 20, 2023
    Inventors: Chih-Yang LOU, Meng-Hua TSAI, Wei-Ting LEE, Sin-Siang WANG
  • Patent number: 11688793
    Abstract: A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao Lu, Chien-I Kuo, LI-Li Su, Wei-Yang Lee, Yee-Chia Yeo
  • Patent number: 11688794
    Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230187518
    Abstract: A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.
    Type: Application
    Filed: April 6, 2022
    Publication date: June 15, 2023
    Inventors: Bo-Yu Lai, Wei-Yang Lee, Ming-Lung Cheng, Chia-Pin Lin, Yuan-Ching Peng
  • Patent number: 11677028
    Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11666234
    Abstract: A blood pressure measurement module includes a base, a valve plate, a top cover, a micro pump, a driving circuit board, and a pressure sensor. The valve plate is disposed between the base and the top cover. The micro pump is in the base. The pressure sensor is disposed on the driving circuit board. An inlet channel of the top cover and the pressure sensor are connected to a gas bag. The micro pump operates to inflate the gas bag to press the skin of a user. The pressure sensor detects a pressure change in the gas bag so as to detect the blood pressure of the user.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 6, 2023
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ching-Sung Lin, Wen-Yang Yang, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee
  • Publication number: 20230134971
    Abstract: Source/drain epitaxial features and methods for fabricating such are disclosed herein. An exemplary method includes receiving a substrate including a n-type region and a p-type region, forming a stack of semiconductor layers over the substrate, the stack of semiconductor layers including interleaving first material layers and second material layers, and performing an etch process to form a first source/drain recess in the n-type region and a second source/drain recess in the p-type region. The method further includes depositing a metal-containing layer over the stack of semiconductor layers, including within the first source/drain recess and the second source/drain recess, removing the metal-containing layer from the n-type region, and forming an n-type epitaxial source/drain feature in the first source/drain recess. The method further includes removing the metal-containing layer from the p-type region and forming a p-type epitaxial source/drain structure in the second source/drain recess.
    Type: Application
    Filed: July 26, 2022
    Publication date: May 4, 2023
    Inventors: Wei-Han Fan, Chia-Pin Lin, Wei-Yang Lee, Tzu-Hua Chiu, I-Hsieh Wong, Alex Lee
  • Publication number: 20230119318
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure extended above a substrate along a first direction, and a first gate structure formed over the first fin structure along a second direction. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first fin structure and adjacent to the first gate structure, and a cap layer formed on and in direct contact with the first S/D structure. The semiconductor device structure includes an isolation structure formed adjacent to the first gate structure and the first S/D structure along the first direction, and a bottom surface of the isolation structure is lower than a bottom surface of the first gate structure and a bottom surface of the first S/D structure.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ching CHU, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Publication number: 20230117516
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Patent number: 11631736
    Abstract: A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Patent number: 11631746
    Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230113464
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure, and a source/drain structure in the fin structure and adjacent to the gate structure. The source/drain structure includes: a first epitaxial layer over the fin structure, a second epitaxial layer over the first epitaxial layer, and an epitaxial capping layer over the second epitaxial layer. The semiconductor structure also includes a silicide layer formed in contact with the source/drain structure. The silicide layer has a curved bottom surface, and the curved bottom surface of the silicide layer intersects with the second epitaxial layer and the epitaxial capping layer.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu LI, Wei-Yang LEE, Wen-Chu HSIAO
  • Patent number: 11626508
    Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yang Lee, Chih-Shan Chen
  • Patent number: 11626505
    Abstract: A semiconductor structure and a method of fabricating thereof is provided. The semiconductor structure may include a plurality of channel layers disposed over a semiconductor substrate, a plurality of metal gate (MGs) each disposed between two channel layers, an inner spacer disposed on a sidewall of each MG, a source/drain (S/D) feature disposed adjacent to the plurality of MGs, and a low-k dielectric feature disposed on the inner spacer, where the low-k dielectric feature extends into the S/D feature. The low-k dielectric feature may include two dissimilar dielectric layers, one of which may be air.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen