Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surfac

Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view. Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from an application processor associated with the UE, an indication of a traffic service type and whether an uplink data stall has occurred. The UE may detect that one or more threshold criteria are satisfied for a serving cell, wherein a threshold value associated with at least one of the one or more threshold criteria is based at least in part on the traffic service type. The UE may transmit information associated with one or more adjusted measurement values of the serving cell based at least in part on detecting that the one or more threshold criteria are satisfied. Numerous other aspects are described.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Abstract: A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.

Abstract: A semiconductor structure includes an active region including a source/drain feature, a contact protruding from a bottom surface of the source/drain feature, a first dielectric layer disposed directly below the active region and surrounding the contact, an air gap disposed between the contact and the first dielectric layer, and a seal disposed between the contact and the first dielectric layer, such that the air gap is disposed between the seal and the source/drain feature.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nanostructures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride and ammonia.

Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

Abstract: A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a PAI process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. A protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. The semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.

Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

Abstract: A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.

Abstract: A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.