Abstract: Semiconductor structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin rising from the substrate, an isolation feature disposed over the substrate and between the first base fin and the second base fin, a first bottom epitaxial feature over the first base fin, a second bottom epitaxial feature over the second base fin, an isolation layer on the first bottom epitaxial feature, a first source/drain feature over the isolation layer, a second source/drain feature disposed over and in contact with the second bottom epitaxial feature, a contact etch stop layer (CESL) over the first source/drain feature and the isolation feature, a first interlayer dielectric (ILD) layer over the CESL, and a second ILD layer over and in direct contact with the second source/drain feature.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

Abstract: According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming an epitaxial stack of channel layers and sacrificial layers on a semiconductor substrate, patterning the epitaxial stack to form a first fin-shape structure in a first region and a second fin-shape structure in a second region, etching the first fin-shape structure to form a first source/drain recess, etching the second fin-shape structure to form a second source/drain recess, forming first inner spacers in the first region, forming second inner spacers in the second region, laterally recessing the second inner spacers, forming a first source/drain feature in the first source/drain recess, and forming a second source/drain feature in the second source/drain recess. After the laterally recessing of the second inner spacers, the second inner spacers have a thickness less than the first inner spacers.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.

Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an inner spacer layer between two adjacent nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the inner spacer layer, and a barrier layer adjacent to the inner spacer layer. The barrier layer extends from the first position to the second position, and the first position is between the inner spacer layer and the nanostructure, and the second position is between the nanostructures and the S/D structure.

Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surfac

Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view. Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.