Patents by Inventor Wei-Yang Lin

Wei-Yang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260205122
    Abstract: This application is directed to electronic systems, devices, circuits, and methods for voltage level shifting. An electronic device includes a pair of current mirroring transistors, which includes a first mirroring transistor and a second mirroring transistor and is configured to mirror a drive current passing the first mirroring transistor to the second mirroring transistor. A pair of differential input transistors is coupled to the pair of current mirroring transistors, includes a first input transistor and a second input transistor, and is configured to receive at least a first input signal. A first swing-clamped transistor is coupled between the second mirroring transistor and the second input transistor, and a gate and a drain of the first swing-clamped transistor are coupled to each other. A first output stage is coupled to the first swing-clamped transistor and configured to generate a first output signal.
    Type: Application
    Filed: December 17, 2024
    Publication date: July 16, 2026
    Inventors: WEI-YANG LIN, KUO-CHENG HUANG, BO-YI KUO, YUEH-LIN Yang
  • Publication number: 20260136994
    Abstract: An electronic package and a manufacturing method thereof are provided, the electronic package has at least one dam at the edge thereof to prevent packaging material from overflowing to the bottom of the electronic package, so that the packaging material is free from contacting the conductive components on the bottom of the electronic package, thereby avoiding problem of non-wetting of the conductive components when the conductive components are subsequently reflowed.
    Type: Application
    Filed: February 20, 2025
    Publication date: May 14, 2026
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Shen HUNG, Wei-Yang LIN
  • Patent number: 9747409
    Abstract: A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 29, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yang Lin, Kai-Ming Liu
  • Publication number: 20170091371
    Abstract: A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: WEI-YANG LIN, KAI-MING LIU
  • Patent number: 8415764
    Abstract: An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Wen Chung, Po-Yao Ke, Wei-Yang Lin, Shine Chung
  • Publication number: 20100301453
    Abstract: An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
    Type: Application
    Filed: March 30, 2010
    Publication date: December 2, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao Wen Chung, Po-Yao Ke, Wei-Yang Lin, Shine Chung
  • Patent number: 7646918
    Abstract: An image is analyzed to locate an object appearing in the image. A contour of that object is extracted from the image and normalized. Based on the normalized contour, one or more summation invariant values are determined and compared to templates comprising one or more summation invariants for each of one or more target objects. The determined summation invariants for the extracted object are compared to summation invariants for the target objects. When the summation invariants for the extracted object sufficiently match the summation invariants determined from an image of a target object, the extracted object is recognized as that target object. The summation invariants can be semi-local summation invariants determined for each point along the normalized contour, based on a number of points neighboring that point on the normalized contour. The semi-local summation invariants are determined as a function of the x and y coordinates of those points.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: January 12, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Wei-Yang Lin, Nigel Boston, Yu Hen Hu
  • Publication number: 20070071325
    Abstract: An image is analyzed to locate an object appearing in the image. A contour of that object is extracted from the image and normalized. Based on the normalized contour, one or more summation invariant values are determined and compared to templates comprising one or more summation invariants for each of one or more target objects. The determined summation invariants for the extracted object are compared to summation invariants for the target objects. When the summation invariants for the extracted object sufficiently match the summation invariants determined from an image of a target object, the extracted object is recognized as that target object. The summation invariants can be semi-local summation invariants determined for each point along the normalized contour, based on a number of points neighboring that point on the normalized contour. The semi-local summation invariants are determined as a function of the x and y coordinates of those points.
    Type: Application
    Filed: January 10, 2006
    Publication date: March 29, 2007
    Inventors: Wei-Yang Lin, Nigel Boston, Yu Hen Hu