Patents by Inventor Wei-Yao Lin
Wei-Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974083Abstract: An electronic device including a protection layer, a display panel, and a sound broadcasting element is provided. The protection layer has an inner surface and a side surface directly connected to the inner surface. The display panel is disposed on the inner surface of the protection layer and has a back surface and a side surface directly connected to the back surface. The sound broadcasting element is located adjacent to the side surface of the display panel, and the sound broadcasting element includes a piezoelectric component and a connection component.Type: GrantFiled: January 12, 2023Date of Patent: April 30, 2024Assignee: Innolux CorporationInventors: Tzu-Pin Hsiao, Wei-Cheng Lee, Jiunn-Shyong Lin, I-An Yao
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Publication number: 20240096893Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
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Patent number: 11935855Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.Type: GrantFiled: November 24, 2021Date of Patent: March 19, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Jen Wang, Yi Dao Wang, Tung Yao Lin
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Patent number: 8817432Abstract: A driver circuit has a pad that may be utilized for programming a core circuit or receiving a data signal. A trace high circuit receives a pad voltage signal from the pad, and outputs a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage. A level shifter and a first inverter output a pull high control signal generated by inverting and level shifting a programming control signal. An ESD blocking circuit selectively blocks the pad voltage signal from reaching the core circuit depending on the pad voltage signal and the level-shifted programming control signal. A pull high circuit receives the pull high control signal and the power supply voltage, and outputs the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.Type: GrantFiled: July 7, 2009Date of Patent: August 26, 2014Assignee: eMemory Technology Inc.Inventors: Shao-Chang Huang, Wei-Yao Lin, Tang-Lung Lee, Kun-Wei Chang
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Publication number: 20140197521Abstract: A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage.Type: ApplicationFiled: January 16, 2013Publication date: July 17, 2014Applicant: ILI TECHNOLOGY CORPORATIONInventors: Wei-Yao LIN, Chung-Wei WANG, Yu-Lun LU, Kuo-Ko CHEN
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Patent number: 8779519Abstract: A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage.Type: GrantFiled: January 16, 2013Date of Patent: July 15, 2014Assignee: Ili Technology CorporationInventors: Wei-Yao Lin, Chung-Wei Wang, Yu-Lun Lu, Kuo-Ko Chen
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Publication number: 20140115622Abstract: An interactive video/image-relevant information embedding technology contains: a server side including a user client-server operation interface module for interacting with the client side; a video/image database for saving videos/images; a label database for saving external information; a video/image content analysis module for segmenting, tracking, recognizing specified items in the videos/images; an external-information retrieval engine for retrieving external information from the public search engine, label database, or additional database; a video/image-external information relation analysis module for creating on-the-fly labels for the specified items in videos/images; a client side which includes: a client-server operation interface module for interacting with the server side; a user operation interface module for interacting with the user/label creator; an original video/image database for saving videos/images; a label information database for saving external information; a video/image content analysisType: ApplicationFiled: October 18, 2012Publication date: April 24, 2014Inventors: Chi-Hsiang Chang, Wei-Yao Lin
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Patent number: 8120984Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.Type: GrantFiled: March 23, 2010Date of Patent: February 21, 2012Assignee: eMemory Technology Inc.Inventors: Shao-Chang Huang, Wei-Yao Lin, Tang-Lung Lee, Kun-Wei Chang, Lin-Fwu Chen, Wen-Hao Lee, Luan-Yi Yen, Yu-Chun Chang
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Publication number: 20110310514Abstract: An electrostatic discharge (ESD) protection circuit is coupled between a first terminal and a second terminal of an integrated circuit. The integrated circuit receives an input signal through the first terminal. The second terminal is coupled to a voltage source. The ESD protection circuit includes a PMOS transistor and a deep N-well NMOS transistor. When the static electricity is inputted to the first terminal, the static electricity flows to the voltage source through the corresponding parasitic diode and the corresponding parasitic bipolar transistor of the PMOS transistor and the deep N-well NMOS transistor. In addition, the input signal is not affected by the ESD protection circuit because the parasitic diodes of the PMOS transistor and the deep N-well NMOS transistor are reversely connected. Thus, the ESD protection circuit prevents the integrated circuit from being damaged by the static electricity and increases the operation voltage range of the input signal.Type: ApplicationFiled: June 17, 2010Publication date: December 22, 2011Inventors: Shao-Chang Huang, Wei-Yao Lin, Tang-Lung Lee, Kun-Wei Chang, Chiun-Chi Shen
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Publication number: 20110235454Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.Type: ApplicationFiled: March 23, 2010Publication date: September 29, 2011Inventors: Shao-Chang Huang, Wei-Yao Lin, Tang-Lung Lee, Kun-Wei Chang, Lin-Fwu Chen, Wen-Hao Lee, Luan-Yi Yen, Yu-Chun Chang
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Patent number: 7965481Abstract: A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.Type: GrantFiled: July 2, 2008Date of Patent: June 21, 2011Assignee: eMemory Technology Inc.Inventors: Shao-Chang Huang, Wei-Yao Lin, Tsung-Mu Lai
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Patent number: 7911752Abstract: An electrostatic discharge (ESD) protection circuit is electrically connected to a core circuit for preventing ESD charges from reaching the core circuit. The ESD protection circuit includes a pad, a pass transistor, a transistor, a capacitor, a resistor, and a delay trigger unit. The pass transistor controls passage of charges from the pad to the core circuit. The transistor sinks ESD charges during an ESD zapping event. The capacitor and the resistor couple voltage at the pad to a control electrode of the transistor for turning on the transistor during the ESD zapping event. The delay trigger unit retards transmission of low voltage to a control electrode of the pass transistor for keeping the pass transistor turned off during the ESD zapping event.Type: GrantFiled: October 29, 2009Date of Patent: March 22, 2011Assignee: eMemory Technology Inc.Inventors: Wei-Yao Lin, Shao-Chang Huang, Mao-Shu Hsu, Tang-Lung Lee, Kun-Wei Chang
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Publication number: 20110063762Abstract: A flash memory circuit with ESD protection includes a plurality of flash memory blocks, a pad, an ESD transistor, a pass transistor, and a gate driving circuit. The gate driving circuit has an inverter circuit for receiving a control voltage and outputting an output voltage, a resistor for receiving a pad voltage from the pad, and a capacitor for delaying a change in the control voltage. The ESD transistor is coupled to the pad, a power supply, and the output terminal of the inverter circuit. The pass transistor is coupled to one of the flash memory blocks and the pad, and is controlled by the output voltage. A well terminal of the pass transistor is coupled to the resistor for keeping the pass transistor turned off during electrostatic discharge through the pad.Type: ApplicationFiled: September 13, 2009Publication date: March 17, 2011Inventors: Tang-Lung Lee, Shao-Chang Huang, Wei-Yao Lin, Kun-Wei Chang
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Publication number: 20100259858Abstract: A driver circuit has a pad that may be utilized for programming a core circuit or receiving a data signal. A trace high circuit receives a pad voltage signal from the pad, and outputs a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage. A level shifter and a first inverter output a pull high control signal generated by inverting and level shifting a programming control signal. An ESD blocking circuit selectively blocks the pad voltage signal from reaching the core circuit depending on the pad voltage signal and the level-shifted programming control signal. A pull high circuit receives the pull high control signal and the power supply voltage, and outputs the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.Type: ApplicationFiled: July 7, 2009Publication date: October 14, 2010Inventors: Shao-Chang Huang, Wei-Yao Lin, Tang-Lung Lee, Kun-Wei Chang
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Publication number: 20100123509Abstract: A pad circuit includes a pad, a gate driving circuit, a voltage selection circuit, and an ESD detection/avoiding circuit. The gate driving circuit is used to discharge the ESD induced current. The ESD detection/avoiding circuit is used to isolate the ESD induced voltage. The voltage selection circuit selects a higher voltage from a power/ground terminal and the pad and outputs it to the gate driving circuit, so that the pad circuit can be used for the programming and 1/0 operations.Type: ApplicationFiled: November 19, 2008Publication date: May 20, 2010Inventors: Wei-Yao Lin, Shao-Chang Huang, Wei-Ming Ku, Tang-Lung Lee, Kun-Wei Chang, Shih-Hsien Wang, Yi-Ling Kuo, Mao-Shu Hsu
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Publication number: 20100002344Abstract: A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.Type: ApplicationFiled: July 2, 2008Publication date: January 7, 2010Inventors: Shao-Chang Huang, Wei-Yao Lin, Tsung-Mu Lai
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Publication number: 20070016318Abstract: A system for managing production availability. A storage device stores a production entry corresponding to a client for production using a particular technology. The production entry comprises a demand profile and a production availability profile. The demand profile specifies the amount of capacity allocated support demand (CASD) for the client during a preset period, comprising a non-booked CASD and a booked CASD. The production availability profile specifies available-to-promise (ATP) production corresponding to the non-booked CASD, comprising production values specifying quantities of ATP production allocated to the client during different divisions of the preset period.Type: ApplicationFiled: July 15, 2005Publication date: January 18, 2007Inventors: Wei-Yao Lin, Rebecca Hsu, Yun-Tzu Chiu
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Patent number: 6799909Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.Type: GrantFiled: April 4, 2003Date of Patent: October 5, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann
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Publication number: 20040115842Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.Type: ApplicationFiled: April 4, 2003Publication date: June 17, 2004Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann
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Patent number: 6280223Abstract: An electrical apparatus in accordance with the present invention for electrically assembling a CPU to a printed circuit board. The CPU includes an array of pin legs. The apparatus comprises a base member securely assembled to the printed circuit board. A cover member is moveably assembled to the base member and defines an array of through holes for extension of the pin legs of the CPU. A driving arrangement is arranged between the base and cover member to drive the cover member to move between first and second positions. The arrangement includes a shaft having a helical section extending therealong, and a follower is moveable along the helical section when the shaft is rotated.Type: GrantFiled: February 9, 2000Date of Patent: August 28, 2001Assignee: Hon Hai Precision Ind. Co., Ltd.Inventor: Wei-Yao Lin