Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

Abstract: Edge devices utilizing personalized machine learning and methods of operating the same are disclosed. An example edge device includes a model accessor to access a first machine learning model from a cloud service provider. A local data interface is to collect local user data. A model trainer is to train the first machine learning model to create a second machine learning model using the local user data. A local permissions data store is to store permissions indicating constraints on the local user data with respect to sharing outside of the edge device. A permissions enforcer is to apply permissions to the local user data to create a sub-set of the local user data to be shared outside of the edge device. A transmitter is to provide the sub-set of the local user data to a public data repository.

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

Abstract: An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

Abstract: Embodiments include apparatuses, methods, and systems to provide an automated loading device to a computer assisted or autonomous driving (CA/AD) vehicle. A loading service control device is to initiate a loading service to load one or more items into a storage space of a CA/AD vehicle, using an automated loading device. A CA/AD vehicle is to move to a loading area at an appointed time. A mechanical loading unit of an automated loading device is to place one or more items into a storage space of a CA/AD vehicle. A user device is to receive an input from a user, where the input includes information to generate a request to a loading service control device to load one or more items into a storage space of a CA/AD vehicle using an automated loading device. Other embodiments may also be described and claimed.

Abstract: Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.

Abstract: A method for operating an SRAM of an FPGA in a high or low-power mode includes a CRAM of the FPGA storing control bits for controlling whether pages of the SRAM operate in the high or low-power mode. A control circuit of the FPGA uses the control bits, a system clock signal, and address for the pages to determine whether to operate the pages in the high or low-power mode and to control the timing for precharging and tristating read bitlines of the pages for the high and low-power modes. In the high-power mode the read bitlines are precharged longer than in the low-power mode, and in the high-power mode the read bitlines are tristated less than in the low-power mode. Precharging the read bitlines for a lesser time in the low-power mode reduces DC leakage current in the lower power mode compared to the high-power mode.

Abstract: An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

Abstract: Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test power-on-reset circuit receives control instructions from the control circuit, and produces a test power-on-reset output according to the control instructions. The integrated circuit includes a logic gate that receives the test power-on-reset output and a power-on-reset signal from the power-on-reset circuit and generates an output signal for bypassing operations of the power-on-reset circuit on the integrated circuit.

Abstract: Example blockchain-based digital data exchanges including example data publisher endpoint devices and example data subscriber endpoint systems are disclosed herein. Example data publisher endpoint devices disclosed herein include a datamart publisher client to transmit a message to a data exchange to publish availability of data to be accessed from data storage associated with the data publisher endpoint device, and in response to a request from a data subscriber endpoint system, initiate a transaction to provide the data subscriber endpoint system with access to the data. Disclosed example data publisher endpoint devices also include a blockchain client to publish a record of the transaction to a blockchain network when the transaction is validated by the datamart publisher client, the record to be included in a blockchain implemented by the blockchain network.

Abstract: Edge devices utilizing personalized machine learning and methods of operating the same are disclosed. An example edge device includes a model accessor to access a first machine learning model from a cloud service provider. A local data interface is to collect local user data. A model trainer is to train the first machine learning model to create a second machine learning model using the local user data. A local permissions data store is to store permissions indicating constraints on the local user data with respect to sharing outside of the edge device. A permissions enforcer is to apply permissions to the local user data to create a sub-set of the local user data to be shared outside of the edge device. A transmitter is to provide the sub-set of the local user data to a public data repository.

Abstract: Embodiments include apparatuses, methods, and systems to provide an automated loading device to a computer assisted or autonomous driving (CA/AD) vehicle. A loading service control device is to initiate a loading service to load one or more items into a storage space of a CA/AD vehicle, using an automated loading device. A CA/AD vehicle is to move to a loading area at an appointed time. A mechanical loading unit of an automated loading device is to place one or more items into a storage space of a CA/AD vehicle. A user device is to receive an input from a user, where the input includes information to generate a request to a loading service control device to load one or more items into a storage space of a CA/AD vehicle using an automated loading device. Other embodiments may also be described and claimed.

Abstract: Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain.

Abstract: Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.

Abstract: Integrated circuits with memory cells are provided. The memory cells may be arranged in rows and columns. Each column of memory cells may be coupled to a respective pair of data lines. The data lines may be precharged using precharge circuitry. The precharge circuitry may include n-channel precharge transistors, an equalizer transistor, an isolation transistor, a pull-down transistor, a voltage booster, and control logic. The voltage booster may provide boosted voltage signal for overdriving the n-channel transistors by pulsing a control signal. During first pulse of the control signal, the data lines may be charged up to an intermediate voltage level. During second pulse of the control signal, the data lines may be charged up to a positive power supply voltage level that is greater than the intermediate voltage level. Performing double boosted data line precharge in this way can help reduce leakage and improve memory performance.

Abstract: An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.

Abstract: Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.