Patents by Inventor Wei-Yeh Tang
Wei-Yeh Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178224Abstract: A method for forming a FinFET device structure is provided. The FinFET device structure includes a first fin structure extending above a substrate, and a first liner layer formed on a first sidewall surface of the first fin structure. The FinFET device structure includes a gate dielectric layer formed over the first fin structure and the first liner layer, wherein a sidewall surface of the gate dielectric layer is aligned with a sidewall surface of the first liner layer.Type: ApplicationFiled: January 31, 2024Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shu WU, Shu-Uei JANG, Wei-Yeh TANG, Ryan Chia-Jen CHEN, An-Chyi WEI
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Patent number: 11923359Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.Type: GrantFiled: July 12, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shu Wu, Shu-Uei Jang, Wei-Yeh Tang, Ryan Chia-Jen Chen, An-Chyi Wei
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Publication number: 20240047581Abstract: A semiconductor structure includes a semiconductor substrate, a gate electrode, a first spacer, and a first contact etch stop layer (CESL). The semiconductor substrate includes a fin structure. The gate electrode is over the fin structure. The first spacer is over the fin structure and on a lateral side of the gate electrode, wherein a top surface of the first spacer is inclined towards the gate electrode. The first CESL is over the fin structure and contacting the first spacer, wherein an angle between the top surface of the first spacer and a sidewall of the first CESL is less than about 140°.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: SHAO-HUA HSU, CHIH-WEI WU, MAO-LIN WENG, WEI-YEH TANG, YEN-CHENG LAI, CHUN-CHAN HSIAO, PO-HSIANG CHUANG, CHIH-LONG CHIANG, YIH-ANN LIN, RYAN CHIA-JEN CHEN
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Publication number: 20210343711Abstract: A method for forming a degreFinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Shu WU, Shu-Uei JANG, Wei-Yeh TANG, Ryan Chia-Jen CHEN, An-Chyi WEI
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Patent number: 11063043Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.Type: GrantFiled: December 12, 2019Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Shu Wu, Shu-Uei Jang, Wei-Yeh Tang, Ryan Chia-Jen Chen, An-Chyi Wei
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Publication number: 20200135725Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.Type: ApplicationFiled: December 12, 2019Publication date: April 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Shu WU, Shu-Uei JANG, Wei-Yeh TANG, Ryan Chia-Jen CHEN, An-Chyi WEI
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Patent number: 10515952Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.Type: GrantFiled: August 4, 2017Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Shu Wu, Shu-Uei Jang, Wei-Yeh Tang, Ryan Chia-Jen Chen, An-Chyi Wei
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Publication number: 20190043857Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.Type: ApplicationFiled: August 4, 2017Publication date: February 7, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Shu WU, Shu-Uei JANG, Wei-Yeh TANG, Ryan Chia-Jen CHEN, An-Chyi WEI
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Patent number: 8334198Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: April 12, 2011Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hao Chen, Wei-Yang Lee, Wei-Yeh Tang, Xiong-Fei Yu, Kuang-Yuan Hsu
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Publication number: 20120264281Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Hao CHEN, Wei-Yang LEE, Wei-Yeh TANG, Xiong-Fei YU, Kuang-Yuan HSU