Patents by Inventor Wei-Yin Chen

Wei-Yin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120388
    Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.
    Type: Application
    Filed: January 18, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240096630
    Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240079239
    Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Inventors: Bau-Ming Wang, Liang-Yin Chen, Wei Tse Hsu, Jung-Tsan Tsai, Ya-Ching Tseng, Chunyii Liu
  • Publication number: 20240072170
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20240074119
    Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.
    Type: Application
    Filed: May 9, 2023
    Publication date: February 29, 2024
    Inventors: Ren-Chun CHANG, Wei-Chih LIN, Sheng-Chi WU, Wen-Yin TSAI, Li-Hsiu CHEN
  • Patent number: 11915942
    Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11886531
    Abstract: A computing device can present, within a display, first network-associated content and a tab strip, the first network-associated content being associated with a first content locator, the tab strip including a first content indicator associated with the first content locator and a second content indicator associated with a second content locator, receive a directional input associated with the tab strip, in response to receiving the directional input, modify the presentation of the tab strip, the modification ending presentation of the first content indicator and initiating presentation of a third content indicator, the third content indicator being associated with a third content locator, receive a selection of the third content indicator, and in response to receiving the selection of the third content indicator, present second network-associated content at a location where the first network-associated content was previously presented, the second network-associated content being associated with the third con
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 30, 2024
    Assignee: GOOGLE LLC
    Inventors: Samuel L. Birch, Yusuf Ozuysal, Christopher Lee, Mei Liang, Wei-Yin Chen, Yue Zhang, Ayman Almadhoun
  • Publication number: 20230372577
    Abstract: Disclosures of the present invention describe a double-layer dressing containing silk fibroin and a method for making the same, wherein the double-layer dressing mainly comprises a silk fibroin layer and a calcium-degradation silk fibroin layer connected to the silk fibroin layer, and it is worth emphasizing that, results of animal experiment have proved that this novel double-layer dressing is an outstanding hemostatic wound dressing; Moreover, additional adhesion, resulted from the solidification of tissue fluid, can be effectively prevented from forming between skin wound and wound dressing under the use of this double-layer dressing.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 23, 2023
    Applicant: LIFE STAR INTERNATIONAL LIMITED
    Inventors: Meng-Yi BAI, Meng-Chuan Chen, Jia-Ying Lin, Wei-Yin Chen
  • Publication number: 20210200832
    Abstract: A computing device can present, within a display, first network-associated content and a tab strip, the first network-associated content being associated with a first content locator, the tab strip including a first content indicator associated with the first content locator and a second content indicator associated with a second content locator, receive a directional input associated with the tab strip, in response to receiving the directional input, modify the presentation of the tab strip, the modification ending presentation of the first content indicator and initiating presentation of a third content indicator, the third content indicator being associated with a third content locator, receive a selection of the third content indicator, and in response to receiving the selection of the third content indicator, present second network-associated content at a location where the first network-associated content was previously presented, the second network-associated content being associated with the third con
    Type: Application
    Filed: December 30, 2020
    Publication date: July 1, 2021
    Inventors: Samuel L. Birch, Yusuf Ozuysal, Christopher Lee, Mei Liang, Wei-Yin Chen, Yue Zhang, Ayman Almadhoun
  • Publication number: 20200188178
    Abstract: Disclosures of the present invention describe a double-layer dressing containing silk fibroin and a method for making the same. The double-layer dressing mainly comprises a silk fibroin layer and a calcium-degradation silk fibroin layer connected to the silk fibroin layer. It is worth emphasizing that, results of animal experiment have proved that this novel double-layer dressing is an outstanding hemostatic wound dressing. Moreover, additional adhesion, resulted from the solidification of tissue fluid, can be effectively prevented from forming between skin wound and wound dressing under the use of this double-layer dressing.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Inventors: MENG-YI BAI, MENG-CHUAN CHEN, JIA-YING LIN, WEI-YIN CHEN
  • Patent number: 8393281
    Abstract: A particle feeder is provided for feeding small particles at a uniform low feed rate. In some embodiments, the particle feeder includes a primary reservoir, a secondary reservoir, and a valve. The primary reservoir encloses an internal volume for holding particles and defining a hole through a bottom surface thereof. The valve includes a rod enclosed within and extending through the volume defined by the primary reservoir. The rod is movable between an open position, wherein particles can flow through the hole, and a closed position, wherein the rod blocks the hole. The actuator controls the movement of the rod between the open position and the closed position. The secondary reservoir has an internal volume, and a conduit for connecting the internal volume of the secondary reservoir with the internal volume of primary reservoir, such that particles can flow from the secondary reservoir into the primary reservoir.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: March 12, 2013
    Assignee: University of Mississippi
    Inventors: Wei-Yin Chen, George Gowan
  • Publication number: 20070034126
    Abstract: A method of reducing nitrogen oxide emissions formed during fuel combustion by introducing biomass ash into a combustion chamber.
    Type: Application
    Filed: June 27, 2006
    Publication date: February 15, 2007
    Inventors: Wei-Yin Chen, Hamid Sarv
  • Patent number: D1017381
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 12, 2024
    Assignee: QBIC TECHNOLOGY CO., LTD.
    Inventors: Yi-Hsin Chen, Wei-Yuan Cheng, Ren-Yin Wu Ji
  • Patent number: D1019349
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 26, 2024
    Assignee: QBIC TECHNOLOGY CO., LTD.
    Inventors: Yi-Hsin Chen, Wei-Yuan Cheng, Ren-Yin Wu Ji