Patents by Inventor Wei-Yu Huang

Wei-Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151394
    Abstract: A device includes first to third power/ground (PG) elements; a first set of at least three tracks between the first and second PG elements and a second set of at least three tracks between the second and third PG elements, the tracks being arranged in equal numbers between the first and second PG and second and third PG elements; a first row of cells overlapping the first set; and a second row of cells overlapping the second set. In the first row of cells, a first cell has a first height and a second cell has a greater height than the first height; in the second row of cells, a third cell has the first height and a fourth cell has a lesser height less than the first height; and a track configured as an in-cell PG track is aligned with a boundary of the second and fourth cells.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventors: Ching-Yu HUANG, Wei-Cheng TZENG, Wei-Cheng LIN, Chia-Tien WU, Ken-Hsien HSIEH, Jiann-Tyng TZENG
  • Publication number: 20250142993
    Abstract: Some embodiments relate to an integrated circuit (IC) device including a substrate having first photodetector groups respectively associated with a plurality of color pixels and second photodetector groups respectively associated with a plurality of phase detection pixels. Each of the first and second photodetector groups includes one or more photodetectors. The device further includes a grid structure over the substrate, color filters over the substrate, and a crosstalk reduction structure. The grid structure includes light shields, each configured to redirect light away from a corresponding one of the second photodetector groups. Each color filter vertically spans the grid structure at a corresponding one of the first photodetector groups. The crosstalk reduction structure is level with the color filters and limits an amount of the light redirected by the light shield of each of the phase detection pixels to the first photodetector group of a neighboring one of the color pixels.
    Type: Application
    Filed: February 26, 2024
    Publication date: May 1, 2025
    Inventors: Yi-Hsuan Wang, Cheng-Yu Huang, Keng-Yu Chou, Wei-Chieh Chiang
  • Publication number: 20250121920
    Abstract: A biomimetic turtle includes a trunk, a head movably connected with a front end of the trunk in the front-rear direction, two front limbs disposed on a front section of the trunk and each rotatable relative to the trunk to sway in an up-down direction, and a driving module to drive the head and the front limbs. Each front limb has a curve-shaped rigid portion with a recess, and a deformable flipper portion engaged in the recess and extending rearwardly. With the deformable flipper portion deformed and bent during swaying of the front limbs, a forward propelling force is generated to propel the biomimetic turtle forwardly. The head is operably movable to vary the center of gravity of 10 the biomimetic turtle 100 in the water, and thus the front portion of the biomimetic turtle is inclined upwardly or downwardly to facilitate ascending or descending of the biomimetic turtle.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 17, 2025
    Inventors: Wei-Yu HUANG, Chang-Qi ZHANG, Guan-Hao PAN, Li-Yuan YEH, Tai-Yu CHEN, Ching-Hung LIU, Jian-Jhih HUANG, Ching-Shu LAI
  • Publication number: 20250123792
    Abstract: A method for handling a display control of a microprocessor in an electronic device includes: receiving a display trigger signal; and controlling a panel device in the electronic device to display a content, in response to the display trigger signal; wherein a central processing unit (CPU) in the electronic device is in a power off state, when controlling the panel device to display the content.
    Type: Application
    Filed: August 25, 2024
    Publication date: April 17, 2025
    Applicant: MEDIATEK INC.
    Inventors: Tsung-Hsin Chen, Chin-Wen Liang, Wei-Chen Lin, Tung-Hung Lin, Shih-Yu Huang, Chen-Wei Yu
  • Publication number: 20250125148
    Abstract: A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chen LEE, Chia-Tien WU, Wei-Chen CHU, Hsi-Wen TIEN, Wei-Cheng TZENG, Ching-Yu HUANG, Wei-Cheng LIN, Ken-Hsien HSIEH
  • Patent number: 12278254
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes forming a first image sensor element within a first substrate and a second image sensor element within a second substrate. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths and the second image sensor element is configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths. A plurality of deposition processes are performed to form a band-pass filter over the second substrate. The band-pass filter has a plurality of alternating layers of a first material having a first refractive index and a second material having a second refractive index that is less than the first refractive index. The first substrate is bonded to the band-pass filter.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Patent number: 12278188
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Patent number: 12278249
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20250116937
    Abstract: A lithography method includes the steps which are mentioned below. A photoresist layer is formed over a substrate. The photoresist layer is exposed. The photoresist layer is developed. A vacuum treatment is performed to the photoresist layer. The substrate is etched by using the photoresist layer as an etch mask.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui WENG, Wei-Han LAI, Hsien-Chung HUANG, Ching-Yu CHANG
  • Publication number: 20250115783
    Abstract: Disclosed herein is a 2K clearcoat coating composition including (A) from 10% to 70% by weight of a first resin having at least one primary hydroxyl group; (B) from 2% to 40% by weight of a second resin including a resin (B-1) having at least one primary hydroxyl group and/or a resin (B-2) having at least one secondary hydroxyl group; and (C) a crosslinker including at least one polyisocyanate and at least one amino resin, and the weight percentages of components (A) and (B) are based on the total weight of the coating composition and the ratio by weight between components (A) and (B) is in a range of from 6:1 to 1:2. Further disclosed herein is an article coated by the coating composition and the article may have metal substrates.
    Type: Application
    Filed: June 14, 2023
    Publication date: April 10, 2025
    Inventors: Yang ZHANG, Wei ZHANG, Lei HE, Jing Yu HUANG, Xiao Gang YOU
  • Patent number: 12272621
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kan-Ju Lin, Lin-Yu Huang, Min-Hsuan Lu, Wei-Yip Loh, Hong-Mao Lee, Harry Chien
  • Patent number: 12272886
    Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: April 8, 2025
    Assignee: IWAVENOLOGY CO., LTD.
    Inventors: Chong-Yi Liou, Wei-Ting Tsai, Jin-Feng Neo, Zheng-An Peng, Tsu-Yu Lo, Zhi-Yao Hong, Tso-An Shang, Je-Yao Chang, Chien-Bang Chen, Shih-Ping Huang, Shau-Gang Mao
  • Publication number: 20250107268
    Abstract: A plurality of holes in a top surface of a silicon medium form a plurality of sub-meta lenses to result in multiple focal points rather than a single point (resulting from using a single meta lens). As a result, optical paths for incoming light are reduced as compared with a single optical path associated with a single meta lens, which in turn reduces angular response of incident photons. Thus, a pixel sensor including the plurality of sub-meta lenses experiences improved light focus and greater signal-to-noise ratio. Additionally, dimensions of the pixel sensor are reduced (particularly a height of the pixel sensor), which allows for greater miniaturization of an image sensor that includes the pixel sensor.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Yi-Hsuan WANG, Cheng Yu HUANG, Chun-Hao CHUANG, Keng-Yu CHOU, Wen-Hau WU, Wei-Chieh CHIANG, Chih-Kung CHANG
  • Patent number: 12261116
    Abstract: In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yu Huang, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng, Yi-Kan Cheng
  • Patent number: 12257612
    Abstract: An apparatus includes a wafer stage and a particle removing assembly. The wafer stage includes a cup adjacent to a wafer chuck. The particle removing assembly is configured to remove contaminant particles from the cup. In some embodiments, the particle removing assembly comprises a flexible ejecting member that includes one or more elongated tubes, a front tip, and a cleaning tip adapter configured to attach the front tip to each of the one or more elongated tubes. The front tip includes front openings and lateral openings from which pressurized cleaning material are introduced onto an unreachable area of the cup to remove the contaminant particles from the cup.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsueh Wu, Fang Yu Kuo, Kai Yu Liu, Yu-Chun Wu, Jau-Sheng Huang, Wei-Yi Chen
  • Patent number: 12258402
    Abstract: The present disclosure relates to a modified antibody, or antigen-binding fragment thereof, specific for nectin cell adhesion molecule 4 (nectin-4). The present disclosure also relates to a method of detecting or diagnosing whether a subject has, or is at risk of developing a tumor, or assessing a prognosis of a tumor and a pharmaceutical composition for use in treating, prophylactic treating and/or preventing tumor in a subject afflicted with the tumor.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: March 25, 2025
    Assignee: NAVI BIO-THERAPEUTICS, INC.
    Inventors: Bor-Yu Tsai, Shin-Tsung Huang, Wei-Ting Hsu
  • Patent number: 12261036
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Publication number: 20250098343
    Abstract: Various embodiments of the present application are directed towards an image sensor including a wavelength tunable narrow band filter, as well as methods for forming the image sensor. In some embodiments, the image sensor includes a substrate, a first photodetector, a second photodetector, and a filter. The first and second photodetectors neighbor in the substrate. The filter overlies the first and second photodetectors and includes a first distributed Bragg reflector (DBR), a second DBR, and a first interlayer between the first and second DBRs. A thickness of the first interlayer has a first thickness value overlying the first photodetector and a second thickness value overlying the second photodetector. In some embodiments, the filter is limited to a single interlayer. In other embodiments the filter further includes a second interlayer defining columnar structures embedded in the first interlayer and having a different refractive index than the first interlayer.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei Chieh Chiang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 12253888
    Abstract: An electronic device including a body and a receptacle connector is provided. The body has a side wall surface, a receptacle slot located at the side wall surface, a waterproof protrusion protruding from the side wall surface, and two gutters located at the side wall surface, where the waterproof protrusion is located above the receptacle slot, and the two gutters are respectively located at two opposite sides of the receptacle slot. The receptacle connector is disposed in the receptacle slot.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: March 18, 2025
    Assignee: Acer Incorporated
    Inventors: Wei-Chih Wang, Chen-Min Hsiu, Chien-Yu Lee, Szu-Wei Yang, Fang-Ying Huang
  • Publication number: 20250089393
    Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu