Abstract: A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal.

Abstract: A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.