Abstract: A light emitting element package includes a first substrate, at least one light emitting element, an encapsulation layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other, in which an edge of the lower surface has a notch. The at least one light emitting element is disposed on the upper surface of the first substrate, in which the light emitting element has a positive electrode and a negative electrode. The encapsulation layer covers the light emitting element. The plurality of conductive pads are disposed on the lower surface of the first substrate and electrically connected to the positive electrode and the negative electrode of the light emitting element, respectively.

Abstract: A tandem solar cell and a method of manufacturing the same are provided. The tandem solar cell includes a bottom solar cell, a silicon suboxide thin film disposed over the bottom solar cell, a transparent conductive thin film disposed over the silicon suboxide thin film, and a top solar cell disposed on the transparent conductive thin film and series connected to the bottom solar cell. The silicon suboxide thin film has a refractive index of 2.0 to 3.5 for a visible light with a wavelength of 700 nm to 750 nm, and the transparent conductive thin film has a refractive index of 1.7 to 2.1 for the visible light with the wavelength of 700 nm to 750 nm. The tandem solar cell can achieve better optical matching and increase conversion efficiency.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A driving mechanism for moving an optical element is provided, including a fixed part, a movable part, a driving assembly, and a first guiding member connected between the fixed part and the movable part. The optical element is disposed on the movable part, and the driving assembly drives the movable part to move relative to the fixed part. The first guiding member is configured for guiding the movable part to move relative to the fixed part.

Abstract: The present disclosure provides an electronic circuit, a memory device, and a method for operating an electronic circuit. An electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.

Abstract: A light emitting element package includes a first substrate, at least one light emitting element, an encapsulation layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other, in which an edge of the lower surface has a notch. The at least one light emitting element is disposed on the upper surface of the first substrate, in which the light emitting element has a positive electrode and a negative electrode. The encapsulation layer covers the light emitting element. The plurality of conductive pads are disposed on the lower surface of the first substrate and electrically connected to the positive electrode and the negative electrode of the light emitting element, respectively.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A selecting method of a non-simplified region of a 3D model of a multilayer metal circuit structure is used for selecting a first non-simplified region in a complete 3D model of a layout design of a multilayer metal circuit structure. The complete 3D model contains multiple layout layers. The electing method of the first non-simplified region includes at least one of first to fourth selecting modes. Through the selecting method of the non-simplified region of the present invention, the entire complete 3D can be effectively simplified in a programmed manner, shortening the overall electrical simulation time.

Abstract: Provide a micro-light-emitting package includes a first substrate, a plurality of micro-light-emitting diodes (micro-LEDs), a transparent protective layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other. The micro-LEDs are disposed on the upper surface of the first substrate. The micro-LEDs have a first electrode and a second electrode electrically opposite to the first electrode. The transparent protective layer covers the micro-LEDs. The plurality of conductive pads are disposed on the lower surface of the first substrate. The conductive pads include a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad. The first conductive pad, the second conductive pad, the third conductive pad respectively electrically connected to the corresponding first electrode of the micro-LEDs. The fourth conductive pad is commonly electrically connected to the second electrode of the plurality of micro-LEDs.

Abstract: An automatically generating method for generating a simulation circuit includes performing a circuit dividing step, a circuit segmenting step, a main element model generating step, a circuit segment model generating step and a model combining step. The circuit dividing step includes accessing a radio frequency circuit information from a memory unit, and dividing the radio frequency circuit information into a plurality of circuit units. The circuit segmenting step includes transforming each of the circuit units into a plurality of circuit segments. The main element model generating step includes generating at least one main element model. The circuit segment model generating step includes generating a circuit segment model. The circuit segment model is corresponding to each of the circuit segments. The model combining step includes combining the at least one main element model and the circuit segment model corresponding to each of the circuit segments to generate the simulation circuit.

Abstract: An excitation source planning method for an electrical stimulation is proposed to plan an excitation source. A layout importing step is performed to drive a processing unit to import a PCB layout to an electromagnetic simulation software module. A port establishing step is performed to set the excitation source to be vertically disposed between a signal layer and a main ground layer. A model generating step is performed to perform the electrical simulation according to the excitation source to generate a three-dimensional simulation model corresponding to the PCB layout. When the signal layer is not electrically connected to the main ground layer, the electromagnetic simulation software module executes an extending step. The extending step is performed to provide a first metal unit to be connected to the signal layer, and reset the excitation source to be vertically disposed between the first metal unit and the main ground layer.

Abstract: An excitation source planning method for an electrical stimulation is proposed to plan an excitation source. A layout importing step is performed to drive a processing unit to import a PCB layout to an electromagnetic simulation software module. A port establishing step is performed to set the excitation source to be vertically disposed between a signal layer and a main ground layer. A model generating step is performed to perform the electrical simulation according to the excitation source to generate a three-dimensional simulation model corresponding to the PCB layout. When the signal layer is not electrically connected to the main ground layer, the electromagnetic simulation software module executes an extending step. The extending step is performed to provide a first metal unit to be connected to the signal layer, and reset the excitation source to be vertically disposed between the first metal unit and the main ground layer.

Abstract: A head mounted device suitable for guiding an exhibition is disclosed. The head mounted device includes an image capturing unit, a process module and an information interface. The process module includes a recognition unit, a computing unit and a control unit. The image capturing unit captures an input image in invisible spectrum. The recognition unit recognizes an invisible code from the input image. The computing unit calculates a relative distance and a relative angle between the head mounted device and an exhibition object. By comparing the relative distance with a threshold distance, the control unit determines whether to trigger the information interface and present an exhibit-object introduction based on relative distance and relative angle.

Abstract: A head mounted device suitable for guiding an exhibition is disclosed. The head mounted device includes an image capturing unit, a process module and an information interface. The process module includes a recognition unit, a computing unit and a control unit. The image capturing unit captures an input image in invisible spectrum. The recognition unit recognizes an invisible code from the input image. The computing unit calculates a relative distance and a relative angle between the head mounted device and an exhibition object. By comparing the relative distance with a threshold distance, the control unit determines whether to trigger the information interface and present an exhibit-object introduction based on relative distance and relative angle.

Abstract: A positive photoresist stripper composition includes a solvent system having solubility parameters which fall within a range from about 8.5 to about 15 in an amount which falls within a range from about 65% to about 98%. An amine is present in an amount which falls within a range from about 2% to about 25%. A fatty acid having 8 to 20 carbon atoms is present in an amount which falls within a range from about 0.1% to about 10% (all percents being by weight). The amount of the amine and of the fatty acid are selected to provide a pH which falls in a range from about 6 to about 9.5. Positive photoresist is stripped from a substrate by immersing the substrate in the aforementioned composition. Metal deposited on the substrate is not attached by the composition.