Abstract: A phase locked loop (PLL) and a voltage controlled oscillator (VCO) thereof are provided. The VCO includes a ring oscillator circuit and a control circuit. The ring oscillator circuit is used for providing an output clock signal; and the control circuit is coupled to the ring oscillator circuit, and used for receiving an output voltage to respectively provide a first voltage-frequency gain and a second voltage-frequency gain so as to control a frequency of the output clock signal provided by the ring oscillator circuit, wherein the first voltage-frequency gain is larger than the second voltage-frequency gain.

Abstract: A transmission driver including a main driving stage and a sub-driving stage is provided. The main driving stage has a main current source, and is adapted for receiving a first differential input data stream and outputting a differential output data stream by using the main current source. The sub-driving stage has two sub-current sources, and is adapted for receiving a second differential input data stream and counteracting/reducing the attenuation or distortion of the differential output data stream caused by a long transmission distance by using the sub-current sources. There is a delay of a specific bit length between the first and the second differential input data streams.

Abstract: A phase locked loop (PLL) and a voltage controlled oscillator (VCO) thereof are provided. The VCO includes a ring oscillator circuit and a control circuit. The ring oscillator circuit is used for providing an output clock signal; and the control circuit is coupled to the ring oscillator circuit, and used for receiving an output voltage to respectively provide a first voltage-frequency gain and a second voltage-frequency gain so as to control a frequency of the output clock signal provided by the ring oscillator circuit, wherein the first voltage-frequency gain is larger than the second voltage-frequency gain.

Abstract: A transceiver that includes a receiver configured to receive a data signal, a controller, a first memory that includes a first table associated with a first set of gain values and a second table associated with a second set of gain values, and a second memory accessible by an external host is provided. The controller is configured to access a first value associated with a strength of the data signal from the receiver, access a second value associated with the first value from the first table, generate a third value using the second value, and store the third value in the second memory.

Abstract: A transceiver that includes a receiver configured to receive a data signal, a controller, a first memory that includes a first table associated with a first set of gain values and a second table associated with a second set of gain values, and a second memory accessible by an external host is provided. The controller is configured to access a first value associated with a strength of the data signal from the receiver, access a second value associated with the first value from the first table, generate a third value using the second value, and store the third value in the second memory.

Abstract: A transceiver that includes a receiver configured to receive a data signal, a controller, a first memory that includes a first table associated with a first set of gain values and a second table associated with a second set of gain values, and a second memory accessible by an external host is provided. The controller is configured to access a first value associated with a strength of the data signal from the receiver, access a second value associated with the first value from the first table, generate a third value using the second value, and store the third value in the second memory.

Abstract: An amplifier includes an amplification path and multiple offset-compensation feedback paths. The amplification path has multiple amplifier stages, and the feedback paths are coupled to the amplification path. By including multiple feedback paths, such an amplifier can maintain its output DC-offset voltage at a desired level over a full range of amplitudes, i.e., power, of the input signal.

Abstract: Systems and methods of recovering a device from a sleep mode of operation are described. In one aspect, a device includes a sleep recovery circuit that is operable to transition from a first signal detection mode to a second signal detection mode in response to detection of a first signal characteristic in an input signal. The sleep recovery circuit also is operable to transition from the second signal detection mode to a third operational mode in response to detection in the input signal of a second signal characteristic different from the first signal characteristic.

Abstract: A transceiver that includes a receiver configured to receive a data signal, a controller, a first memory that includes a first table associated with a first set of gain values and a second table associated with a second set of gain values, and a second memory accessible by an external host is provided. The controller is configured to access a first value associated with a strength of the data signal from the receiver, access a second value associated with the first value from the first table, generate a third value using the second value, and store the third value in the second memory.