Abstract: An amplifier circuit is provided. The amplifier circuit comprises a first transconductance amplifier and a first transimpedance amplifier. The first transconductance amplifier receives a first input signal. A first input terminal of the first transimpedance amplifier is coupled to a first input terminal of the first transconductance amplifier. The first transimpedance amplifier comprises a first resistor and a first inverter. The first resistor is coupled between a first output terminal of the first transimpedance amplifier and the first input terminal of the first transimpedance amplifier. An output terminal of the first inverter is coupled to the first input terminal of the first transimpedance amplifier.

Abstract: The computing in memory device includes a memory circuit, a word line driver circuit, a detection circuit and a voltage modulation circuit. The memory circuit includes memory blocks arranged in parallel and coupled to each other through bit lines. Each memory block has memory cells respectively coupled to the bit lines. A word line and a power line couple the memory cells. The word line driving circuit generates an analog driving current according to the binary input value to drive the memory cells through the word line. The detection circuit detects this analog drive current. The voltage modulation circuit detects change of the output current based on the analog driving current to generate an operating voltage to provide to the memory cells through the power line.

Abstract: A differential channel circuit structure is disclosed. The differential channel circuit structure comprises a first differential circuit including a differential channel and a termination circuit. The differential channel has a differential mode impedance and a common mode impedance, and includes a first end and a second end, each capable of processing at least a first differential signal and a first common mode signal. The termination circuit includes a third end and a fourth end connected to the first end and the second end of the differential channel respectively, so as to simultaneously match the differential mode impedance and the common mode impedance of the differential channel.

Abstract: A high speed transceiver includes an analog front-end circuit, a feed-forward equalizer, a decision feedback equalizer, an SNR estimation circuit, and a channel measurement circuit. The analog front-end circuit preprocesses the received signal from the channel, which is then transmitted to the feed-forward equalizer for equalization. The decision feedback equalizer processes the output of the feed-forward equalizer to mitigate post-cursor inter-symbol interference. The channel measurement circuit uses signals from the analog front-end circuit and decision feedback equalizer to extract the single pulse response. The SNR estimator evaluates the receiver noise performance based on the difference between the output and input of the decision feedback equalizer. The output from the channel measurement circuit is used to optimize the settings of the equalizers.

Abstract: A multi-level pulse amplitude modulation (PAM) signal receiving device comprises an all transition phase detector (ATPD) for receiving a data signal. The ATPD comprises a first-layer comparator structure to compare the data signal with critical voltages of the first-layer comparator structure to generate an error information, and a second-layer comparator structure connected to the first-layer comparator structure in series to compare reset speeds of the first-layer comparator structure to generate a data information. A decoder coupled to the ATPD for decoding the data information to generate a binary code. A least mean square engine coupled to the ATPD for updating the critical voltages based on the error information.

Abstract: A differential channel circuit structure is disclosed. The differential channel circuit structure comprises a first differential circuit including a differential channel and a termination circuit. The differential channel has a differential mode impedance and a common mode impedance, and includes a first end and a second end, each capable of processing at least a first differential signal and a first common mode signal. The termination circuit includes a third end and a fourth end connected to the first end and the second end of the differential channel respectively, so as to simultaneously match the differential mode impedance and the common mode impedance of the differential channel.

Abstract: A memory array for computing-in-memory (CIM) is disclosed. The memory array for CIM includes a bit cell array, at least one word line and at least one bit line. The bit cell array has a plurality of bit cells, wherein each bit cell is operated at an operating voltage. The at least one word line is electrically connected to the bit cell array, wherein the at least one word line is associated with a first parameter. The at least one bit line is electrically connected to the bit cell array, wherein the bit cells extend along a specific direction, each the at least one bit line has an electrical parameter associated therewith, each the bit cell is associated with a second parameter, a first quantity of the plurality of bit cells of the bit cell array extends along the specific direction, and the memory array determines how an expansion associated with at least one of the first parameter and the second parameter is according to the specific direction.

Abstract: A computing-in-memory apparatus is provided, which includes a voltage regulator having an amplifier and a reference current source, a computing-in-memory array having a plurality of computing units and a detection circuit connected to each other. The amplifier has a current input and a voltage output and is connected to the reference current source, and the voltage regulator provides an output voltage for supplying to the computing-in-memory array. An output current of the detection circuit is inputted into the voltage regulator to compare with the reference current source of the voltage regulator, and then a negative feedback convergence or a negative feedback mechanism is executed according to the comparison result to regulate the output voltage supplied by the voltage regulator to the computing-in-memory array.

Abstract: A computing-in-memory apparatus is provided, which includes a voltage regulator having an amplifier and a reference current source, a computing-in-memory array having a plurality of computing units and a detection circuit connected to each other. The amplifier has a current input and a voltage output and is connected to the reference current source, and the voltage regulator provides an output voltage for supplying to the computing-in-memory array. An output current of the detection circuit is inputted into the voltage regulator to compare with the reference current source of the voltage regulator, and then a negative feedback convergence or a negative feedback mechanism is executed according to the comparison result to regulate the output voltage supplied by the voltage regulator to the computing-in-memory array.

Abstract: A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased.

Abstract: A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.

Abstract: A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.

Abstract: A wireless receiving device includes a wake-up receiver, a main receiver and a calibration circuit. The wake-up receiver operates in a monitoring mode or a sleep mode. When operating in the monitoring mode, the wake-up receiver monitors whether a request signal is transmitted by a communication device and issues a wake-up signal after receiving the request signal. The main receiver operates in a sleep mode or a transmission mode. When operating in the sleep mode, the main receiver is woken up and enters the transmission mode to transmit and receive data to and from the communication device when receiving the wake-up signal. The calibration circuit is coupled to the wake-up receiver and the main receiver and configured to receive a calibration signal from the main receiver and calibrate a reception frequency of the wake-up receiver in the background in response to the calibration signal.

Abstract: A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased.

Abstract: A multi-level pulse-amplitude modulation receiver system includes an analog equalizer, a digital equalizer, an automatic level tracking engine and an automatic gain controller. The analog equalizer and the automatic gain controller perform signal compensation on a multi-bit quasi-attenuation signal to generate a multi-level compensation signal. The digital equalizer receives the multi-level compensation signal, the positive threshold voltage and the negative threshold voltage, and thereby converts the multi-level compensation signal into a plurality of digital data. The automatic level tracking engine uses the digital data to generate a positive threshold voltage, a negative threshold voltage, at least two positive DC level voltages, and at least two negative DC level voltages, and the positive threshold voltage is an average of the two positive DC level voltages to avoid the nonlinear effect of the analog front end.

Abstract: A readout circuit of a touch panel is provided. The readout circuit includes a charge modulator and a correlated double sampling demodulator. The charge modulator is configured to provide a driving current to charge or discharge a sensing electrode of the touch panel and generate a sensing voltage signal. The correlated double sampling demodulator is coupled to the charge modulator. The correlated double sampling demodulator is configured to sample the sensing voltage signal to obtain a voltage variation when a touch event happens. A method for driving the touch panel is also provided.

Abstract: A wireless receiving device includes a wake-up receiver, a main receiver and a calibration circuit. The wake-up receiver operates in a monitoring mode or a sleep mode. When operating in the monitoring mode, the wake-up receiver monitors whether a request signal is transmitted by a communication device and issues a wake-up signal after receiving the request signal. The main receiver operates in a sleep mode or a transmission mode. When operating in the sleep mode, the main receiver is woken up and enters the transmission mode to transmit and receive data to and from the communication device when receiving the wake-up signal. The calibration circuit is coupled to the wake-up receiver and the main receiver and configured to receive a calibration signal from the main receiver and calibrate a reception frequency of the wake-up receiver in the background in response to the calibration signal.

Abstract: A readout circuit of a touch panel is provided. The readout circuit includes a charge modulator and a correlated double sampling demodulator. The charge modulator is configured to provide a driving current to charge or discharge a sensing electrode of the touch panel and generate a sensing voltage signal. The correlated double sampling demodulator is coupled to the charge modulator. The correlated double sampling demodulator is configured to sample the sensing voltage signal to obtain a voltage variation when a touch event happens. A method for driving the touch panel is also provided.

Abstract: A lower limb rehabilitation system includes an analysis platform, a smart insole, a motion sensor and a brain wave sensor. The analysis platform has a deep learning model. The smart insole generates plural pressure signals through plural pressure sensors of a pressure sensing film. The smart insole includes a processing unit controlling a transmission unit to transmit the pressure signals to the analysis platform. The processing unit is connected to a power supply unit. The motion sensor generates a motion signal. The brain wave sensor is coupled with the analysis platform and detects a brain wave signal. The analysis platform inputs the pressure signals, the motion signal and the brain wave signal into the deep learning model for analyzing a gait. The deep learning model analyzes whether the gait is correct. The analysis platform generates a warning message if the gait is analyzed to be incorrect.

Abstract: A frequency synthesizer and a method for frequency synthesis are provided. The frequency synthesizer includes a subband phase-locked loop (PLL) and a main PLL. A divisor of an adjustable non-integer frequency divider in the subband PLL is adjusted, and a channel frequency of a maximum frequency band of all frequency bands is output. A divisor of an adjustable integer frequency divider in the main PLL is adjusted, and a center frequency required for each frequency band of the all frequency bands is output. The center frequency and the channel frequency are mixed by a mixer to produce a band frequency. A quantization noise generated by the adjustable non-integer frequency divider is filtered out by the subband PLL to reduce the impact of the quantization noise on the main PLL.