Abstract: An application interface layout method includes that a developer sets a layout container having an adaptive layout capability in a layout file of an application, where the adaptive layout capability includes at least one of an extension capability, a proportion capability, an equalization capability, a wrapping capability, a hiding capability, a stretching capability, or a scaling capability. In this way, when running the application, an electronic device arranges, based on a screen parameter of the electronic device and the adaptive layout capability of the layout container in the layout file, a size and a location of a child view in the layout container on a display interface.

Abstract: The present disclosure provides a method of manufacturing semiconductor structure. The method includes providing a substrate, including an active area and an isolation surrounding the active area; forming a trench fuse in the active area; forming a gate structure of a transistor over the substrate adjacent to the trench fuse; and forming a doping region surrounding the trench fuse and the gate structure; wherein a distance between the isolation and the trench fuse is less than a distance between the isolation and the gate structure.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

Abstract: A method includes following steps. A target layer is formed over a substrate. A first hard mask layer is formed over the target layer by a plasma generated using a first radio frequency generator and a second radio frequency generator. The first radio frequency generator and the second radio frequency generator have different powers. A second hard mask layer is formed over the first hard mask layer by a plasma generated using the first radio frequency generator without using the second radio frequency generator. A photoresist layer is formed over the second hard mask layer. The photoresist layer is exposed. The photoresist layer is developed. The first hard mask layer and the second hard mask layer are patterned using the photoresist layer as an etch mask. The target layer is patterned using the first hard mask layer and the second hard mask layer as an etch mask.

Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums that that utilize targeted telemetry in a highly complex UI such as a 3D UI using dynamic object references, subscription-based retrieval, and hierarchical object model to provide advanced telemetry streams. These streams may be used in accurately diagnosing issues in real-time for highly complex UI environments, such as 3D communication systems. While a 3DCS is used herein as an example of an environment to which the present disclosure is applicable, one of ordinary skill in the art with the benefit of the present disclosure will appreciate that the techniques described here may be applied to other highly complex and dynamic environments as well.

Abstract: The present disclosure discloses a preparation method for 6-substituted chiral pure difluoropiperidine quinazoline derivative, in particular the 6-substituted chiral pure difluoropiperidine quinazoline derivative shown in Formula (I). The preparation method provided by the present disclosure is characterized by high chiral selectivity, high yield, and good process stability, which is of great significance for further production scale-up and commercialization of said solid drugs.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source/drain (S/D) region, and a resistance modification doped region. The well region is within the substrate with a first conductive type. The fuse medium is disposed over the substrate. The gate electrode is disposed over the fuse medium. The fuse doped region is under the gate electrode with a second conductive type different from first conductive type. The S/D region is adjacent to the fuse doped region with the second conductive type. The resistance modification doped region has the second conductive type and partially overlaps the fuse doped region.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source/drain (S/D) region, and a resistance modification doped region. The well region is within the substrate with a first conductive type. The fuse medium is disposed over the substrate. The gate electrode is disposed over the fuse medium. The fuse doped region is under the gate electrode with a second conductive type different from first conductive type. The S/D region is adjacent to the fuse doped region with the second conductive type. The resistance modification doped region has the second conductive type and partially overlaps the fuse doped region.

Abstract: A light emitting substrate is provided. The light emitting substrate includes light emitting elements of multiple types. The light emitting elements of different types are configured to emit light of a same color but different wavelength ranges. Light emitting elements of a respective type of the light emitting elements of multiple types are substantially evenly distributed in the light emitting substrate.

Abstract: A testing module includes a wafer and a probe head. The wafer includes a scribe line and a probe pad. The scribe line extends along a direction. The probe pad is disposed on the scribe line. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion. The first portion includes a trench exposing the dielectric layer, and the second portion is disposed on the first recess and a top surface of the dielectric layer to form a first via. The probe head includes multiple probe needles.

Abstract: Provided are a display panel and a manufacturing method thereof, a display device and a spliced display device. The display panel includes: a color filter substrate (11), an array substrate (12) and a first conductive portion (13), where a display region (AA) and a peripheral region (NA) are formed on the display panel, and the peripheral region (NA) surrounds the display region (AA); the array substrate (12) includes pixel circuits and a second conductive portion (14), where the pixel circuits are located in the display region (AA), and the second conductive portion (14) is located in the peripheral region (NA); the second conductive portion (14) is connected with the pixel circuits; the first conductive portion (13) is located on a side surface of the array substrate (12) and a side surface of the color filter substrate (11), and the first conductive portion (13) is connected with the second conductive portion (14).

Abstract: A fabrication method includes: forming, above a substrate, a first electrode having a varying density that increases from a first density level at a bottom surface of the first electrode to a second density level that is higher than the first density level at a top surface of the first electrode; forming a high-K dielectric layer over the first electrode; and forming a second electrode over the HK dielectric layer having a varying density that increases from a third density level at a bottom surface of the second electrode that bonds to the HK dielectric layer to a fourth density level that is higher than the third density level at a top surface of the second electrode.

Abstract: Provided a separator, a preparation method therefor, a secondary battery and a power consuming device. The separator comprises a first substrate layer, a mixed material layer and a second substrate layer; the mixed material layer is provided between the first substrate layer and the second substrate layer; the mixed material layer comprises an inorganic material and a dispersant. The separator of the present application can delay the occurrence of lithium dendrites or sodium dendrites puncturing the separator and the occurrence of internal short circuit in the battery, prolong the service life of the battery, increase the infiltration of the separator to the electrolyte solution and the charge and discharge rate of the battery, improve the thermal shrinkage performance of the battery, and increase the safety and the first coulombic efficiency of the battery.

Abstract: An electronic device receives a first plurality of images of a scene captured by an image sensor of an electronic device, receives an ambient light level proximate to the electronic device, and determines whether the ambient light level is less than a first threshold value. In accordance with a determination that the ambient light level is less than the first threshold value, the electronic device detects motion in the scene based on one or more of the first plurality of images. In accordance with detecting motion in the scene, the electronic device receives a second plurality of images of the scene captured by the image sensor of the electronic device, forms a composite image from two or more of the second plurality of images, and causes the composite image to be presented for display on a user device.

Abstract: A display device and a display driving method are provided. In a display module, sub-pixels of a same color in adjacent rows are arranged in a staggered manner. The method includes: pre-storing a correspondence between a position of a sub-pixel in a bright-dark boundary region and a corresponding target gray-scale value, wherein a distance between the bright-dark boundary region and a boundary line of bright and dark pixels is within a predefined threshold, the bright and dark pixels are adjacent sub-pixels whose initial gray-scale difference is greater than a first predetermined gray-scale difference, and the correspondence is that the closer the position of the sub-pixel is to the boundary line of the bright and dark pixels, the lower the target gray-scale value is; and determining a current gray-scale value of the sub-pixel in the bright-dark boundary region according to the pre-stored correspondence.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: This invention provides an asymmetric pads structure using at a scribe line of a wafer, comprising a test element device electrically connected to a first pad and a second pad separately, wherein a first spacing between the second pad and the test element device is sufficient to accommodate the second pad of an another asymmetric pads structure. So, two neighboring asymmetric pads structures may cross to each other to form a cross configuration.

Abstract: The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.