Abstract: Some disclosed embodiments are directed to computing systems having different accelerators such that a first set of accelerators has a greater memory capability than a second set accelerators, while the second set of accelerators has a greater processing capability than the first set of accelerators. A machine learning model having different dense layers and sparse layers is distributed on the different accelerators such that the dense layers are distributed on one or more accelerators selected from the first set of accelerators and the sparse layers are distributed on one or more accelerators in the second set of accelerators.

Abstract: Some disclosed embodiments are directed to computing systems having different accelerators such that a first set of accelerators has a greater memory capability than a second set accelerators, while the second set of accelerators has a greater processing capability than the first set of accelerators. A machine learning model having different dense layers and sparse layers is distributed on the different accelerators such that the dense layers are distributed on one or more accelerators selected from the first set of accelerators and the sparse layers are distributed on one or more accelerators in the second set of accelerators.

Abstract: A substrate of a circuit board and a substrate of a charging coil are disposed at a same layer, a first wiring layer and a first coil are disposed at a same layer, and a second wiring layer and a second coil are disposed at a same layer, so that the charging coil and the circuit board form an integrated structure. The first coil and the second coil may be directly electrically connected to a wire on the circuit board, for example, a wire at the first wiring layer of the circuit board or a wire at the second wiring layer of the circuit board. This can shorten a charging path between the charging coil and a load, to reduce a link loss. In addition, a BTB connector can be omitted, to simplify a structure of a charging coil module, and reduce costs of the charging coil module.

Abstract: The present invention discloses a graph partitioning system for running neural networks on resource constrained hardware systems. The graph partitioning system used for partitioning a neural network graph into a series of sub-graphs and further allow the multiple sub-graphs to be executed in available hardware subsystems. The system based on cost function as estimated computation time and memory bandwidth of partitioned sub-graphs. The graph partitioning system is a cycle estimation model of hardware that can run fast and parameterize memory latency. The graph partitioning system supports heterogeneous partition for different type accelerators such as CPU, GPU, ASIC. The present invention also discloses a method for partitioning neural network graph in to series of sub-graphs.

Abstract: Systems and methods for identifying scripts by coding style. A system can include one or more processors, coupled to memory. The system can identify a script for execution by a computing device of an entity. The system can determine, via a model trained with machine learning based on a plurality of scripts established by a plurality of entities, a classification of the script prior to execution of the script by the computing device. The system can control execution of the script responsive to the classification of the script.

Abstract: Some disclosed embodiments are directed to computing systems having different accelerators such that a first set of accelerators has a greater memory capability than a second set accelerators, while the second set of accelerators has a greater processing capability than the first set of accelerators. A machine learning model having different dense layers and sparse layers is distributed on the different accelerators such that the dense layers are distributed on one or more accelerators selected from the first set of accelerators and the sparse layers are distributed on one or more accelerators in the second set of accelerators.

Abstract: A computing device may include a memory and a processor coupled to the memory and configured to collect usage activity data across a plurality of different applications for a plurality of users, and determine different groups of users based upon cluster modeling of the usage activity data. The processor may further determine respective application priorities for the applications for each group of users based upon the usage activity data for the group of users, determine computing resource allocations for the applications of each group of users based upon the application priorities for the group of users, and run applications for the users with the computing resource allocations for the respective group of users applied thereto.

Abstract: The present invention discloses a graph partitioning system for running neural networks on resource constrained hardware systems. The graph partitioning system used for partitioning a neural network graph into a series of sub-graphs and further allow the multiple sub-graphs to be executed in available hardware subsystems. The system based on cost function as estimated computation time and memory bandwidth of partitioned sub-graphs. The graph partitioning system is a cycle estimation model of hardware that can run fast and parameterize memory latency. The graph partitioning system supports heterogeneous partition for different type accelerators such as CPU, GPU, ASIC. The present invention also discloses a method for partitioning neural network graph in to series of sub-graphs.

Abstract: A method of constructing sub-graphs, includes receiving a directed acyclic graph (DAG), partitioning the directed acyclic graph into an at least one section, determining at least one hardware attribute, determining at least one DAG hardware limitation of the at least one section and determining a largest continuous node list of the at least one section in which the at least one hardware attribute meets the at least one DAG hardware limitation.

Abstract: Disclosed is a method for culturing urine-derived kidney stem cells, which belongs to the field of cell biology. The method comprises the following steps: isolating cells from the urine, and then culturing the cells with a culture medium of urine-derived kidney stem cells on feeder cells to obtain the urine-derived kidney stem cells, wherein the feeder cells are fibroblasts, and the culture medium of urine-derived kidney stem cells contains 200-300 mL of DMEM medium, 200-300 mL of F12 medium, 20-70 mL of fetal bovine serum, 0.2-2 mM of L-glutamine, 1-14 ng/mL of insulin, 0.1-1 ng/mL of epidermal growth factor, 5-30 ?g/mL of adenine, and 2-20 ?g/mL of hydrocortisone. By using the method, kidney stem cells with high proliferation capacity and specificity can be obtained and applied, and thus the regenerative outcome of the kidney tissue after injury can be improved.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: Embodiments of the present invention provide efficient and automatic systems and methods for regulating the viewing posture of a user. Embodiments of the present invention can be used to regulate the viewing posture of both juveniles and adults, by providing real-time data analysis of a viewing distance and viewing angle of a device, and generating feedback to a user related to their current viewing posture, while also providing increased supervision of the viewing posture of juvenile device users.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: Embodiments of the present invention provide efficient and automatic systems and methods for regulating the viewing posture of a user. Embodiments of the present invention can be used to regulate the viewing posture of both juveniles and adults, by providing real-time data analysis of a viewing distance and viewing angle of a device, and generating feedback to a user related to their current viewing posture, while also providing increased supervision of the viewing posture of juvenile device users.

Abstract: A virus detection engine determines that a file is suspected of being malware. A property is retrieved, along with the same file property of other executable files within the same folder. If the property value is similar to property values of the other files then the suspect file is benign. If the number of matches is greater than a threshold then the suspect file is benign. Other file properties of the suspect file are compared. If no file properties are similar to properties of the other files then the suspect file is malware and an alert is generated. The longest common subsequence compares property values. The same property value may be added to files within the same folder after these files are installed on the computer but before any detection takes place. A comparison of the same property values concludes that files are not malware, even if they are suspect.

Abstract: Embodiments of the present invention provide efficient and automatic systems and methods for regulating the viewing posture of a user. Embodiments of the present invention can be used to regulate the viewing posture of both juveniles and adults, by providing real-time data analysis of a viewing distance and viewing angle of a device, and generating feedback to a user related to their current viewing posture, while also providing increased supervision of the viewing posture of juvenile device users.

Abstract: Embodiments of the present invention provide efficient and automatic systems and methods for regulating the viewing posture of a user. Embodiments of the present invention can be used to regulate the viewing posture of both juveniles and adults, by providing real-time data analysis of a viewing distance and viewing angle of a device, and generating feedback to a user related to their current viewing posture, while also providing increased supervision of the viewing posture of juvenile device users.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.