Abstract: The present invention discloses a signal skew measurement method for integrated circuit, a medium, and an electronic device. The method comprises: by a test machine, acquiring a first signal and a second signal output by an IC, respectively performing under-sampling on the first and second signals to obtain a first sampled signal and a second sampled signal; respectively performing digital conversion on the first and second sampled signals based on a preset threshold voltage to obtain a first digital signal and a second digital signal; respectively performing convolution on the first and second digital signals using a preset pulse signal to obtain a first comparison signal and a second comparison signal; and calculating a skew between the first and second comparison signals to obtain a reference skew, and determining a skew between the first and second signals according to the reference skew.

Abstract: The present invention discloses a signal skew measurement method for integrated circuit, a medium, and an electronic device. The method comprises: by a test machine, acquiring a first signal and a second signal output by an IC, respectively performing under-sampling on the first and second signals to obtain a first sampled signal and a second sampled signal; respectively performing digital conversion on the first and second sampled signals based on a preset threshold voltage to obtain a first digital signal and a second digital signal; respectively performing convolution on the first and second digital signals using a preset pulse signal to obtain a first comparison signal and a second comparison signal; and calculating a skew between the first and second comparison signals to obtain a reference skew, and determining a skew between the first and second signals according to the reference skew.

Abstract: A semiconductor chip and a circuit and a method for electrically testing a semiconductor chip are disclosed, which pertain to the field of semiconductor technology. The semiconductor chip includes: a first electrical connection point, configured to connect a first pole of a force power supply in a Kelvin testing circuit; and a second electrical connection point, configured to connect a first terminal of a detecting device in the Kelvin testing circuit, wherein the first electrical connection point and the second electrical connection point are connected with each other within the semiconductor chip, and the first pole of the force power supply and the first terminal of the detecting device are arranged on the same side of the Kelvin testing circuit. According to the present disclosure, the semiconductor chip can be electrically tested with an enhanced accuracy and no impact from external contact and conduction resistances.