Abstract: A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion.

Abstract: A gain controlled voltage controlled oscillator. A current controlled oscillator is adapted to provide an output signal oscillating at a frequency controllable by controlling a current applied thereto. A first current source provides a first control current controllable by controlling a voltage applied thereto that has a predetermined range. A first current mirror is adapted to mirror the control current to the current controlled oscillator. A second current source is adapted to provide a second control current for mirroring to the current controlled oscillator by the first current mirror when the control voltage is in a low portion of the range.

Abstract: A Sigma-Delta Analog-to-Digital Converter (ADC) having efficient dithering that removes the idle channel tones of the sigma-delta converter is disclosed herein. These idle channel tones are reduced or removed by stretching the threshold window of the multi-level quantizer. A dithering sequence is added by stretching the thresholds window randomly. The randomly stretched window destructs the periodicity of sigma-delta ADC modulator's output sequence and, thus, removes the idle channel tones. Compared with conventional methods, the Sigma-Delta ADC in accordance with the present invention has less SNR penalty and is simple to implement. Moreover, the sigma-delta ADC in accordance with the present invention has a higher allowed input dynamic range and higher signal-to-noise-plus-distortion-ratio (SNDR) than conventional modulator dithering schemes.

Abstract: In accordance with a preferred embodiment, a self-calibrated cell (and corresponding operation) is provided that receives a reference parameter (e.g., current, voltage, etc.) for storage in the cell and for supplying to a load. The individual cell is controlled to operate in different states or modes: either a redundant mode or a supplying mode. In the redundant mode, the reference parameter is stored in the current cell during a calibration phase or mode, and the stored reference parameter is dumped or otherwise transferred, preferably to ground, during a dumping state or mode. In the supplying mode, the current cell transfers or supplies the stored reference parameter to the load. The individual cell is controlled to operate in its dumping state both before the cell enters the calibration mode and also at the same time that the cell is switched from the calibration mode to the supplying mode. In accordance with a preferred embodiment, the individual cells may be employed in a cell array of a converter (e.g.

Abstract: A method of configuring a switch-network to implement programmable gain devices such as Programmable Gain Amplifiers (PGAs). The method provides high-accuracy and low-distortion with small area requirements and less sensitivity to process and temperature variations when compared with traditional programmable gain architectures where the gain is determined by a ratio between one or more fixed resistors and one or more programmable resistors.

Abstract: In accordance with a preferred embodiment, a self-calibrated cell (and corresponding operation) is provided that receives a reference parameter (e.g., current, voltage, etc.) for storage in the cell and for supplying to a load. The individual cell is controlled to operate in different states or modes: either a redundant mode or a supplying mode. In the redundant mode, the reference parameter is stored in the current cell during a calibration phase or mode, and the stored reference parameter is dumped or otherwise transferred, preferably to ground, during a dumping state or mode. In the supplying mode, the current cell transfers or supplies the stored reference parameter to the load. The individual cell is controlled to operate in its dumping state both before the cell enters the calibration mode and also at the same time that the cell is switched from the calibration mode to the supplying mode. In accordance with a preferred embodiment, the individual cells may be employed in a cell array of a converter (e.g.

Abstract: A pipelined analog-to-digital converter includes a first stage 700 of an analog-to-digital converter having a first resolution. The first stage 700 includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages 200. The first and subsequent stages 700 and 200 are pipelined together to provide a digital output signal.