Abstract: This application provides a method for information recommendation performed by an electronic device.

Abstract: A display panel and a drive method therefor, where when a gate electrode drive circuit (100) scans pixels line-by-line, a drive chip (300) controls a clock signal end to input a clock control signal (CK) into the gate electrode drive circuit (100), which causes a gate electrode scan signal (G(n)) to be output by the gate electrode drive circuit (100), and a data signal (Vd) output by a data signal end is controlled to be written to a corresponding row of pixel circuits (200). Where an active level period of the clock control signal (CK) falls within an active level period of the data signal (Vd), and a start time for the active level period of the data signal (Vd) is at least 1-2 ?s earlier than a start time for the active level period of the clock control signal (CK).

Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

Abstract: Devices and methods for analog to digital conversion are provided. The device can have a supply voltage coupled to a bootstrap circuit operable to provide a boosted voltage during a first period defined by a sample phase (Ps) signal and a hold phase (Ph) signal. The device can also have a sampling circuit having an input node and operable to sample an input signal supplied to the input node. The device can also have a switching circuit having a first switch and a second switch. The switching circuit can be coupled to the bootstrap circuit and to the sampling circuit. The switching circuit can be configured to isolate the input node from shorting currents to the supply voltage for a portion of the first period.