Patents by Inventor Weichao Xu
Weichao Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10829390Abstract: Disclosed is a multilayer body, comprising a base (2) and a carbon material layer (1) on the base (2), wherein the base (2) is water-permeable, and the carbon material comprises one or more of the following materials: graphite, graphene, graphene oxide, a chemical function group-modified graphene and carbon nanotubes. Further disclosed are a method for preparing the multilayer body, the use of the multilayer body, and a light-absorbing device containing the multilayer body.Type: GrantFiled: April 11, 2017Date of Patent: November 10, 2020Assignee: NANJING UNIVERSITYInventors: Jia Zhu, Xiuqiang Li, Weichao Xu
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Patent number: 10784848Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.Type: GrantFiled: November 19, 2019Date of Patent: September 22, 2020Assignees: Northwestern University, Regent of the University of MinnesotaInventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
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Publication number: 20200091904Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.Type: ApplicationFiled: November 19, 2019Publication date: March 19, 2020Applicant: Northwestern UniversityInventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
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Patent number: 10491206Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.Type: GrantFiled: February 15, 2018Date of Patent: November 26, 2019Assignee: Northwestern UniversityInventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
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Publication number: 20190106335Abstract: Disclosed is a multilayer body, comprising a base (2) and a carbon material layer (1) on the base (2), wherein the base (2) is water-permeable, and the carbon material comprises one or more of the following materials: graphite, graphene, graphene oxide, a chemical function group-modified graphene and carbon nanotubes. Further disclosed are a method for preparing the multilayer body, the use of the multilayer body, and a light-absorbing device containing the multilayer body.Type: ApplicationFiled: April 11, 2017Publication date: April 11, 2019Inventors: Jia Zhu, Xiuqiang Li, Weichao Xu
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Publication number: 20180183423Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.Type: ApplicationFiled: February 15, 2018Publication date: June 28, 2018Applicants: Northwestern University, Regents of the University of MinnesotaInventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
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Patent number: 9947724Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.Type: GrantFiled: February 20, 2017Date of Patent: April 17, 2018Assignees: NORTHWESTERN UNIVERSITY, REGENTS OF THE UNIVERSITY OF MINNESOTAInventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
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Patent number: 9929725Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.Type: GrantFiled: December 28, 2015Date of Patent: March 27, 2018Assignees: Northwestern University, Regents of the University of MinnesotaInventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
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Publication number: 20170162628Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.Type: ApplicationFiled: February 20, 2017Publication date: June 8, 2017Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
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Patent number: 9613879Abstract: In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.Type: GrantFiled: October 10, 2014Date of Patent: April 4, 2017Assignees: NORTHWESTERN UNIVERSITY, REGENTS OF THE UNIVERITY OF MINNESOTAInventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
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Publication number: 20160204773Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.Type: ApplicationFiled: December 28, 2015Publication date: July 14, 2016Inventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
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Publication number: 20150102288Abstract: In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.Type: ApplicationFiled: October 10, 2014Publication date: April 16, 2015Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
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Publication number: 20030216654Abstract: A method for accurate and rapid automated detection of atrial fibrillation (AF), sinus rhythm (SF), and atrial flutter (AFL) is disclosed, which allows distinguishing of these cardiac signals with lowered risk of errors by implanted pacemakers and like devices. The method includes training episodes of intra-cardiac signals (called the closed data set CDS) to evaluate five feature parameters with a discriminator classifying the signal into AF, AFL or sinus rhythm (SR). Comparison with the independent decisions of experienced physicians for each episode reveals specificity, accuracy and sensitivity of greater than 97%. Each episode is a window of intracardiac signal of interval 1-2 seconds with the discriminator providing results in less than 0.25 s. In another aspect, the method is resistant to the presence of noise in the data. In yet another aspect, more feature parameters may be used in alternative implementations including for detecting signals other than AF, AFL & SR.Type: ApplicationFiled: May 7, 2002Publication date: November 20, 2003Inventors: Weichao Xu, Hung-Fat Tse, Francis Hy Chan, Peter Chin Wan Fung, Chu-pak Lau