Abstract: The present invention discloses a CSS-PD (Charge-Steering-Sampling Phase Discriminator), a DLF (Digital Loop Filter) and a CSS-ADPLL (Charge-Steering-Sampling All Digital Phase-Locked Loop) thereof The CSS-PD includes a Frac-N C-DAC, a CSS, and a SAR-ADC. The CSS-PD has a controlling method including four steps: (1) charge presetting; (2) charge-steering sampling; (3) fractional charge compensating; (4) digitalizing. Wherein when ?Verr,pn sampled by the CSS included two errors ?Verr,pn and ?Verr,frac, ?Verr,frac had fractional charge compensating by setting part of the capacitors of the Cfrac of the Frac-N C-DAC to a Vref,adc. Vref,adc was satisfied the following formula: ?Verr,frac=Dfrac·Cunit/(Cfrac+Csar)·Vref,adc. Cunit is for capacitance of Cfrac, Cfrac is also for capacitance of Cfrac, Csar is also for capacitance of Csar of the SAR-ADC, Dfrac is the output signal of the Frac-N C-DAC.

Abstract: The present invention discloses a CSS-PD (Charge-Steering-Sampling Phase Discriminator), a DLF (Digital Loop Filter) and a CSS-ADPLL (Charge-Steering-Sampling All Digital Phase-Locked Loop) thereof The CSS-PD includes a Frac-N C-DAC, a CSS, and a SAR-ADC. The CSS-PD has a controlling method including four steps: (1) charge presetting; (2) charge-steering sampling; (3) fractional charge compensating; (4) digitalizing. Wherein when ?Verr,pn sampled by the CSS included two errors ?Verr,pn and ?Verr,frac, ?Verr,frac had fractional charge compensating by setting part of the capacitors of the Cfrac of the Frac-N C-DAC to a Vref,adc. Vref,adc was satisfied the following formula: ?Verr,frac=Dfrac·Cunit/(Cfrac+Csar)·Vref,adc. Cunit is for capacitance of Cfrac, Cfrac is also for capacitance of Cfrac, Csar is also for capacitance of Csar of the SAR-ADC, Dfrac is the output signal of the Frac-N C-DAC.