Patents by Inventor Weiching Horng

Weiching Horng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6225219
    Abstract: A method of stabilizing an anti-reflection coating (ARC) layer is disclosed. The method provides a substrate with a dielectric layer, a conductive layer, and the ARC layer formed thereon. The ARC layer is treated in an alloy treatment step prior to forming a photoresist layer over the ARC layer, so that the specificity of the ARC layer is stabilized to allow accurate transfer of a desired pattern. A photomask with the desired pattern is provided, while a photolithographic process is then performed to transfer the pattern onto the wafer.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: May 1, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Kan-Yuan Lee, Weiching Horng, Joe Ko, Gary Hong
  • Patent number: 6221761
    Abstract: A method of stabilizing an anti-reflection coating (ARC) layer is disclosed. The method provides a substrate with a dielectric layer, a conductive layer, and the ARC layer formed thereon. The ARC layer is treated in an ultraviolet (UV) curing step prior to forming a photoresist layer over the ARC layer, so that the specificity of the ARC layer is stabilized to allow an accurate pattern is replicated in the photoresist layer. A photomask with the desired pattern is provided, while a photolithographic process is then performed to transfer the pattern onto the wafer.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: April 24, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Kan-Yuan Lee, Weiching Horng, Joe Ko, Gary Hong
  • Patent number: 6103577
    Abstract: A flash memory structure is formed by a method comprising the steps of providing a semiconductor substrate, and then forming a shallow first trench within the substrate. Thereafter, a buried doped region is formed underneath the first trench so that the buried doped region is at a distance from the substrate surface. The buried doped region is one major aspect in this invention that can be applied to the processing of shallow trench isolation and is capable of reducing device area. Next, a deeper second trench is etched in the substrate. The second trench has a greater depth than the depth of the first trench. Subsequently, insulating material is deposited into the first and the second trench, and then a stacked gate structure is formed above the substrate. Later, the surface source region and drain region are formed on two sides of the stacked gate structure. Through thermal operation, the surface source region alternately connects with the buried doped region to form a buried common source region.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: August 15, 2000
    Assignee: United Semiconductor Corp.
    Inventor: Weiching Horng