Patents by Inventor Wei-Chung Chen

Wei-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12166096
    Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan
  • Publication number: 20240404877
    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
    Type: Application
    Filed: July 25, 2024
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
  • Patent number: 12152101
    Abstract: Disclosed are support-activators and catalyst compositions comprising the support-activators for polymerizing olefins in which the support-activator includes clay heteroadduct, prepare from a colloidal phyllosilicate such as a colloidal smectite clay, which is chemically-modified with a heterocoagulation agent. By limiting the amount of heterocoagulation reagent relative to the colloidal smectite clay as described herein, the smectite heteroadduct support-activator is a porous and amorphous solid which can be readily isolated from the resulting slurry by a conventional filtration process, and which can activate metallocenes and related catalysts toward olefin polymerization. Related compositions and processes are disclosed.
    Type: Grant
    Filed: October 11, 2023
    Date of Patent: November 26, 2024
    Assignee: FORMOSA PLASTICS CORPORATION, U.S.A.
    Inventors: Michael D Jensen, Kevin Chung, Daoyong Wang, Wei-Chun Shih, Guangxue Xu, Chih-Jian Chen, Charles R. Johnson, II, Mary Lou Cowen
  • Publication number: 20240385507
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20240387397
    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
    Type: Application
    Filed: July 27, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20240379672
    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Patent number: 12129864
    Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.
    Type: Grant
    Filed: December 13, 2023
    Date of Patent: October 29, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-I Ling, Chao-Fu Yang, Chih-Chung Chen, Kuo-Tung Hsu
  • Patent number: 12124163
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20240345764
    Abstract: A memory control circuit unit, a memory storage device, and a parameter updating method are disclosed. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The memory interface is configured to be coupled to a rewritable non-volatile memory module. The memory management circuit is configured to detect system status and activate an interface parameter updating operation in response to the system status meeting a target condition. The memory management circuit is further configured to update at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module during the interface parameter updating operation.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 17, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Patent number: 12117043
    Abstract: An air-floating guide rail device includes a guide rail unit, a slider unit, and a linear motor unit. The guide rail unit includes a guide rail body and two air-floating block sets made of a material different from that of the guide rail body and each including top and side air-floating blocks. The slider unit includes a main sliding seat and two lateral sliding seats connected integrally to the main sliding seat and each having first and second guiding surfaces transverse to each other and disposed respectively adjacent to corresponding top and side air-floating blocks, and first and second air guiding passages connecting the first and second guiding surfaces to the external environment. The linear motor unit includes a stator and a mover mounted fixedly to the main sliding seat and movable relative to the stator for driving linear movement of the slider unit relative to the guide rail unit.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: October 15, 2024
    Assignee: Toyo Nano System Corporation
    Inventors: Kun-Cheng Tseng, Kuei-Tun Teng, Wei-Chih Chen, Wen-Chung Lin
  • Publication number: 20240339756
    Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation patch conductive layer, a parasitic patch conductive layer and a ground conductive layer. The radiation patch conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer is a ring structure. The parasitic patch conductive layer is disposed on the dielectric substrate. The ground conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer, the parasitic patch conductive layer and the ground conductive layer are composed of a plurality of wires interconnected and connected with each other and are light-transmissive.
    Type: Application
    Filed: April 2, 2024
    Publication date: October 10, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bing-Syun LI, Li-Yang TSAI, Kuang-Hui SHIH, Ruo-Lan CHANG, Wei-Chung CHEN
  • Publication number: 20240339758
    Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation conductive layer and a ground conductive layer. The dielectric substrate has a first surface and a second surface. The radiation conductive layer is disposed on the first surface of the dielectric substrate. The ground conductive layer is disposed on the second surface of the dielectric substrate. The radiation conductive layer and the ground conductive layer are composed of a plurality of wires connected in a mesh manner. Each of the wires is composed of a plurality of grid lines connected in a mesh manner.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 10, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bing-Syun LI, Li-Yang TSAI, Kuang-Hui SHIH, Ruo-Lan CHANG, Kung-Ching CHU, Wei-Chung CHEN
  • Patent number: 12112516
    Abstract: A non-intrusive detection method for detecting at least one pop-up window button of the pop-up window includes the following steps: retrieving a screen image on a display device; comparing the screen image with a preset screen image and generating a differential image area according the screen image and the preset screen image; determining the differential image area as the pop-up window when the differential image area is greater than an image area threshold value; selecting a plurality of contour lengths of the pop-up window matching up with a contour length threshold value by Canny edge detector; and analyzing the contour lengths according to Douglas-Peucker algorithm and an amount of endpoints to generate a contour edge corresponding to the pop-up window button.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: October 8, 2024
    Assignee: ADLINK Technology Inc.
    Inventors: Chien-Chung Lin, Wei-Jyun Tu, Yu-Yen Chen
  • Patent number: 12106473
    Abstract: A medical image analyzing system and a medical image analyzing method are provided and include inputting at least one patient image into a first model of a neural network module to obtain a result having determined positions and ranges of an organ and a tumor of the patient image; inputting the result into a second model of a first analysis module and a third model of a second analysis module, respectively, to obtain at least one first prediction value and at least one second prediction value corresponding to the patient image; and outputting a determined result based on the first prediction value and the second prediction value. Further, processes between the first model, the second model and the third model can be automated, thereby improving identification rate of pancreatic cancer.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: October 1, 2024
    Assignee: National Taiwan University
    Inventors: Wei-Chung Wang, Wei-Chih Liao, Kao-Lang Liu, Po-Ting Chen, Po-Chuan Wang, Da-Wei Chang
  • Patent number: 12107336
    Abstract: A broadband linear polarization antenna structure, including a reference conductive layer, a first patch antenna, a second patch antenna, and a feeding portion, is provided. The reference conductive layer includes through holes. A first short pin is connected between the reference conductive layer and the first patch antenna, and a second short pin is connected between the first patch antenna and the second patch antenna. Each feeding portion penetrates the reference conductive layer through the through hole and is coupled to the first patch antenna.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 1, 2024
    Assignee: TMY Technology Inc.
    Inventors: Yang Tai, Shun-Chung Kuo, Wen-Tsai Tsai, An-Ting Hsiao, Wei-Yang Chen, Jiun-Wei Wu
  • Publication number: 20240324090
    Abstract: A metal reuse system for an extreme ultra violet (EUV) radiation source apparatus includes a first metal collector for collecting metal from vanes of the EUV radiation source apparatus, a first metal storage coupled to the first metal collector via a first conduit, a metal droplet generator coupled to the first metal storage via a second conduit, and a first metal filtration device disposed on either one of the first conduit and the second conduit.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Shin CHENG, Han-Lung CHANG, Li-Jui CHEN, Po-Chung CHENG, Hsiao-Lun CHANG
  • Patent number: 12099366
    Abstract: A system for obstacle detection adapted to a self-guiding machine is provided. The system includes a controller, a linear light source and a light sensor. The linear light source and the light sensor are set apart at a distance. When the linear light source emits an indicator light being a vertical linear light projected onto a path the self-guiding machine travels toward, the light sensor senses the indicator light. The vertical linear light is segmented into a first segment projected to a ground and a second segment projected to a floating obstacle when the self-guiding machine approaches the floating obstacle with a height from the ground and the indicator light is projected to the floating obstacle, in which the second segment of the light sensed by the light sensor is determined as the floating obstacle in front of the self-guiding machine.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: September 24, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Kai-Shun Chen, Wei-Chung Wang
  • Publication number: 20240304575
    Abstract: A bonding structure for connecting a chip and a metal material, and a manufacturing method thereof are provided. The bonding structure includes a substrate, a chip, a metal member, at least one metal wire and an alloy connection layer. An upper surface of the substrate has a first metal pad and a second metal pad. The chip is disposed on the first metal pad. The metal member is disposed above the chip. The at least one metal wire has a first end and a second end, the first end is connected to an upper surface of the metal piece, and the second end is connected to the second metal pad. The alloy connection layer is connected between the metal member and the chip, and covers at least a part of a lower surface of the metal member.
    Type: Application
    Filed: November 22, 2023
    Publication date: September 12, 2024
    Inventors: ZZU-CHI CHIU, WEI-CHUNG CHAO, YAN-WEI CHEN
  • Patent number: 12067717
    Abstract: A medical image analyzing system and a medical image analyzing method are provided and include inputting at least one patient image into a first model of a first neural network module to obtain a result having determined positions and ranges of an organ and a tumor of the patient image; inputting the result into a plurality of second models of a second neural network module, respectively, to obtain a plurality of prediction values corresponding to each of the plurality of second models and a model number predicting having cancer in the plurality of prediction values; and outputting a determined result based on the model number predicting having cancer and a number threshold value. Further, processes between the first model and the second models can be automated, thereby improving identification rate of pancreatic cancer.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: August 20, 2024
    Assignee: National Taiwan University
    Inventors: Wei-Chung Wang, Wei-Chih Liao, Kao-Lang Liu, Po-Ting Chen, Po-Chuan Wang, Ting-Hui Wu
  • Publication number: 20240274441
    Abstract: A method for forming a semiconductor device includes providing a substrate that has a first region and a second region adjacent to the first region; forming several first components on the substrate and in the first region, and forming a second component on the substrate and in the second region; forming a first material layer over the first components to cover the first components; and forming a patterned dummy layer that is embedded in the first material layer; forming a second material layer over the second component to cover the second component; and performing a polishing process on the first material layer and the second material layer simultaneously. The second material layer and the first material layer include different materials.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 15, 2024
    Inventors: Wei-Nan CHUANG, Yu-Ting HUANG, Yi-Chung CHEN