Abstract: A system and method for chemical mechanical polishing (“CMP”) pad replacement on a CMP processing tool. A platen carrier having two or more platens is positioned within a platen cleaning process module. Each platen includes a CMP pad affixed thereto, and is capable of being independently rotated during operations. When a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. A pad tape replacement module is positioned above the CMP tool with pad tape extending from a supply roll to a recycle roll. As the pad tape transits through the module, a backing of the tape is separated and recycled. A pad disposed in the pad tape is then applied to a platen via a pressure roller.

Abstract: An antenna device based on a transparent substrate and a method of configuring an antenna device are provided. The antenna device includes a transparent substrate, a first dielectric layer, and an antenna. The transparent substrate includes a first surface and a second surface opposite to the first surface. The first dielectric layer includes a third surface and a fourth surface opposite to the third surface, wherein the first dielectric layer is in contact with the first surface via the third surface to be disposed on the transparent substrate, wherein a permittivity of the first dielectric layer is less than a permittivity of the transparent substrate. The antenna includes a radiation part, wherein the radiation part is disposed on one of the second surface and the fourth surface.

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer on the gate structure, forming a patterned mask on the gate structure and one side of the gate structure, removing the first spacer on another side of the gate structure, and then forming a source/drain region adjacent to two sides of the gate structure.

Abstract: An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the fir

Abstract: A walking aid comprises a first foot stand mechanism and a second foot stand mechanism that are spaced apart and have unequal widths and heights, and a grip rod mechanism and a crossover rod mechanism spanning between the first foot stand mechanism and the second foot stand mechanism. The first foot stand mechanism comprises two first foot pole modules spaced apart at front and back, and a first upper rod and a first cross rod spaced apart at top and bottom and spanning between the two first foot pole modules. The second foot stand mechanism comprises two second foot pole modules spaced apart at front and back, and a second upper rod and a second cross rod spaced apart at top and bottom and spanning between the two second foot pole modules.

Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.

Abstract: A method for diagnosing a reason of a malfunction is provided. The method includes: receiving a signal to be diagnosed; decomposing the signal to be diagnosed into a plurality of sub-signals; transforming each of the plurality of sub-signals into a corresponding grayscale image; and inputting the corresponding grayscale images to a neural network model, and outputting a malfunction reason classification result through the neural network model. Accordingly, the method can be used for diagnosing the reason of the malfunction and solves the problem of incapable of diagnosing the reason of the malfunction. In addition, a device and a computer-readable recording medium for diagnosing the reason of the malfunction are also provided.

Abstract: A method for forming an interconnection structure includes depositing a dielectric layer over a first interconnect layer, wherein the first interconnect layer comprises a first metallization layer; forming a via opening in the dielectric layer, and forming a conductive via in the via opening. Forming the via opening includes: etching a recess in the dielectric layer above the first metallization layer; etching a first lateral recess in the dielectric layer at a sidewall of the recess; and after etching the first lateral recess, etching the recess downward to expose the first metallization layer.

Abstract: A system and method for chemical mechanical polishing (“CMP”) pad replacement on a CMP processing tool. A platen carrier having two or more platens is positioned within a platen cleaning process module. Each platen includes a CMP pad affixed thereto, and is capable of being independently rotated during operations. When a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. A pad tape replacement module is positioned above the CMP tool with pad tape extending from a supply roll to a recycle roll. As the pad tape transits through the module, a backing of the tape is separated and recycled. A pad disposed in the pad tape is then applied to a platen via a pressure roller.

Abstract: A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.

Abstract: An electronic device includes a transparent substrate, a number of pixel structures and a first trace structure. The transparent substrate includes a transparent region and a trace region. Each of the pixel structures has a sub-pixel structure of first color and a sub-pixel structure of second color. The sub-pixel structure of first color has a light emitting element of first color. The sub-pixel structure of second color has a light emitting element of second color. The first trace structure includes a first main trace, a first auxiliary trace and a second auxiliary trace. The first main trace is disposed in the trace region and surrounds a portion of the transparent region. The first auxiliary trace and the second auxiliary trace are electrically connected to the first main trace, and are electrically connected to the corresponding sub-pixel structure of first color and the corresponding sub-pixel structure of second color, respectively.

Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation patch conductive layer, a parasitic patch conductive layer and a ground conductive layer. The radiation patch conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer is a ring structure. The parasitic patch conductive layer is disposed on the dielectric substrate. The ground conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer, the parasitic patch conductive layer and the ground conductive layer are composed of a plurality of wires interconnected and connected with each other and are light-transmissive.

Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation conductive layer and a ground conductive layer. The dielectric substrate has a first surface and a second surface. The radiation conductive layer is disposed on the first surface of the dielectric substrate. The ground conductive layer is disposed on the second surface of the dielectric substrate. The radiation conductive layer and the ground conductive layer are composed of a plurality of wires connected in a mesh manner. Each of the wires is composed of a plurality of grid lines connected in a mesh manner.

Abstract: The present disclosure provides a latch mechanism, applied to a rack-mount server system. The rack-mount server system includes a server and a manifold, and the server includes a casing and a fluid connector. The manifold includes a manifold connector. The latch mechanism includes a fixing member, a fixing frame and a hook member. The fixing member is disposed on the manifold and includes a fixing pin. The fixing frame is secured to the server and includes a shaft. The hook member is rotatably disposed on the shaft and includes a hook portion. By rotating the hook portion to latch with the fixing pin, the fixing frame and fixing member are secured with each other, and the fluid connector of the server is coupled to and in fluid communication with the manifold connector of the manifold.

Abstract: An antenna device based on a transparent substrate and a method of configuring an antenna device are provided. The antenna device includes a transparent substrate, a first dielectric layer, and an antenna. The transparent substrate includes a first surface and a second surface opposite to the first surface. The first dielectric layer includes a third surface and a fourth surface opposite to the third surface, wherein the first dielectric layer is in contact with the first surface via the third surface to be disposed on the transparent substrate, wherein a permittivity of the first dielectric layer is less than a permittivity of the transparent substrate. The antenna includes a radiation part, wherein the radiation part is disposed on one of the second surface and the fourth surface.