Abstract: A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell.

Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Abstract: Some of the embodiments of the present disclosure provide a transistor comprising a p-type well; and an n-type well; wherein at least a part of one of the p-type well and the n-type well overlaps with at least a part of another of the p-type well and the n-type well. Other embodiments are also described and claimed.

Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Abstract: An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

Abstract: A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

Abstract: An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

Abstract: A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

Abstract: An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.

Abstract: A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.

Abstract: A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.

Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.

Abstract: An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the carbon content of the dielectric material in two regions of the integrated circuit structure. The first region comprises the region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines, while the second region comprises the region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the dielectric layer to an overlying layer of metal interconnects.

Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.

Abstract: An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.

Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.

Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.