Abstract: Provided are a gene detection kit and a gene detection device. The gene detection kit includes a kit body, a piston cylinder, and a piston. The kit body has an accommodating cavity and a plurality of reagent cavities. The piston cylinder is provided in the accommodating cavity, and the piston cylinder has a piston cavity. The piston is movably provided in the piston cavity along an axial direction of the piston cylinder. A first channel in communication with the piston cavity is provided on an outer circumferential surface of the piston cylinder, a plurality of second channels are provided on an inner wall of the accommodating cavity, each of the second channels is in corresponding communication with one of the reagent cavities, and the piston cylinder can move relative to the kit body, so that the plurality of second channels are alternately in communication with the first channel.

Abstract: A test circuit includes a signal processor, a first resistor, a second resistor, a first switch, and a second switch. The signal processor is coupled to a first drive end, a second drive end, a first sensing end, and a second sensing end. The first resistor is coupled between the first drive end and the first sensing end. The second resistor is coupled between the second drive end and the second sensing end. The first switch is coupled between the first sensing end and a first end of a device under test. The second switch is coupled between the second sensing end and a second end of the device under test. The first drive end is coupled to the first end of the device through a first transmission wire, and the second drive end is coupled to the second end of the device through a second transmission wire.

Abstract: Provided are a gene detection kit and a gene detection device. The gene detection kit includes a kit body, a piston cylinder, and a piston. The kit body has an accommodating cavity and a plurality of reagent cavities. The piston cylinder is provided in the accommodating cavity, and the piston cylinder has a piston cavity. The piston is movably provided in the piston cavity along an axial direction of the piston cylinder. A first channel in communication with the piston cavity is provided on an outer circumferential surface of the piston cylinder, a plurality of second channels are provided on an inner wall of the accommodating cavity, each of the second channels is in corresponding communication with one of the reagent cavities, and the piston cylinder can move relative to the kit body, so that the plurality of second channels are alternately in communication with the first channel.

Abstract: The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.

Abstract: The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.

Abstract: A semiconductor package includes a semiconductor die, a tab, a first lead, and a continuous lead frame. The semiconductor die includes a first terminal, a second terminal, and a third terminal. The tab is electronically coupled to the first terminal. The semiconductor die is mounted on the tab. The first lead is electronically coupled to the second terminal. The continuous lead frame is electronically coupled to the third terminal and includes a second lead and a third lead.

Abstract: A power conversion circuit is provided. The circuit includes an isolated board mounted power module operable to convert a nominal input voltage into an intermediate bus voltage; the board mounted power module being unregulated and controlled in an open-loop; and a plurality of tightly regulated point-of-load converters operable to convert the intermediate bus voltage into respective point-of-load voltages to power a respective number of loads.

Abstract: A method and circuit arrangement for achieving zero voltage switching (ZVS) in a 50% duty cycle full-bridge DC bus converter. The ZVS is obtained by increasing the transformer magnetizing current. During the small dead time between conductions of the two bridge legs, the increased magnetizing current supports the output inductor current, and resonates with MOSFET output capacitance, resulting in ZVS operation. With ZVS operation, body diode conduction and voltage spikes across the secondary synchronous rectifiers are reduced, full load efficiency is increased, and transformer flux balance is enhanced.

Abstract: ORing diodes are used for power redundancy. In order to reduce the power loss due to the diode forward drop voltage, active ORing power MOSFETs are proposed to replace the diodes. With the active ORing controller and power MOSFETs, the power loss can be easily decreased by 90%. To make an N-channel MOSFET work like a diode when it is in reverse and have a very small forward voltage drop when it is in forward, an ORing controller is provided. Its offset, hysteresis, and propagation delay times are optimized for speed, stability, and noise immunity. Its ORing function is tested in an ORing demo board. Its FET check feature makes a live checkup of the ORing power MOSFETs to improve the reliability of the redundant power system.

Abstract: ORing diodes are used for power redundancy. In order to reduce the power loss due to the diode forward drop voltage, active ORing power MOSFETs are proposed to replace the diodes. With the active ORing controller and power MOSFETs, the power loss can be easily decreased by 90%. To make an N-channel MOSFET work like a diode when it is in reverse and have a very small forward voltage drop when it is in forward, an ORing controller is provided. Its offset, hysteresis, and propagation delay times are optimized for speed, stability, and noise immunity. Its ORing function is tested in an ORing demo board. Its FET check feature makes a live checkup of the ORing power MOSFETs to improve the reliability of the redundant power system.

Abstract: A power conversion circuit is provided. The circuit includes an isolated board mounted power module operable to convert a nominal input voltage into an intermediate bus voltage; the board mounted power module being unregulated and controlled in an open-loop; and a plurality of tightly regulated point-of-load converters operable to convert the intermediate bus voltage into respective point-of-load voltages to power a respective number of loads.