Patents by Inventor Weidong Qian
Weidong Qian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8319301Abstract: An image sensor includes at least one photosensitive element disposed in a semiconductor substrate. Metal conductors may be disposed on the semiconductor substrate. A filter may be disposed between at least two individual metal conductors and a micro-lens may be disposed on the filter. There may be insulator material disposed between the metal conductors and the semiconductor substrate and/or between individual metal conductors. The insulator material may be removed so that the filter may be disposed on the semiconductor substrate.Type: GrantFiled: February 11, 2008Date of Patent: November 27, 2012Assignee: OmniVision Technologies, Inc.Inventors: Hsin-Chih Tai, Duli Mao, Vincent Venezia, WeiDong Qian, Ashish Shah, Howard E. Rhodes
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Patent number: 8097890Abstract: An image sensor having a plurality of micro-lenses disposed on a semiconductor substrate. A first micro-lens has a different focal length, height, shape, curvature, thickness, etc., than a second micro-lens. The image sensor may be back side illuminated or front side illuminated.Type: GrantFiled: February 11, 2008Date of Patent: January 17, 2012Assignee: OmniVision Technologies, Inc.Inventors: WeiDong Qian, Hsin-Chih Tai, Vincent Venezia, Howard E. Rhodes
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Patent number: 7972948Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.Type: GrantFiled: September 13, 2010Date of Patent: July 5, 2011Assignee: Spansion LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
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Patent number: 7888269Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.Type: GrantFiled: October 24, 2005Date of Patent: February 15, 2011Assignees: Spansion LLC, GlobalFoundries, Inc.Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher H. Raeder, Christopher Foster, Weidong Qian, Minh Van Ngo
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Publication number: 20100330762Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width.Type: ApplicationFiled: September 13, 2010Publication date: December 30, 2010Applicant: SPANSION LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
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Patent number: 7811915Abstract: A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.Type: GrantFiled: March 14, 2008Date of Patent: October 12, 2010Assignee: Spansion LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
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Publication number: 20090200623Abstract: An image sensor having a plurality of micro-lenses disposed on a semiconductor substrate. A first micro-lens has a different focal length, height, shape, curvature, thickness, etc., than a second micro-lens. The image sensor may be back side illuminated or front side illuminated.Type: ApplicationFiled: February 11, 2008Publication date: August 13, 2009Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: WeiDong Qian, Hsin-Chih Tai, Vincent Venezia, Howard E. Rhodes
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Publication number: 20090200622Abstract: An image sensor includes at least one photosensitive element disposed in a semiconductor substrate. Metal conductors may be disposed on the semiconductor substrate. A filter may be disposed between at least two individual metal conductors and a micro-lens may be disposed on the filter. There may be insulator material disposed between the metal conductors and the semiconductor substrate and/or between individual metal conductors. The insulator material may be removed so that the filter may be disposed on the semiconductor substrate.Type: ApplicationFiled: February 11, 2008Publication date: August 13, 2009Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Hsin-Chih Tai, Duli Mao, Vincent Venezia, WeiDong Qian, Ashish Shah, Howard E. Rhodes
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Patent number: 7465644Abstract: A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical isolation region formed in the exposed portion of the semiconducting layer, where the isolation region does not substantially encroach a region beneath the layer of aluminum oxide.Type: GrantFiled: October 26, 2005Date of Patent: December 16, 2008Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Simon S. Chan, Weidong Qian, Scott Bell, Phillip Jones, Allison Holbrook
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Patent number: 7432178Abstract: A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.Type: GrantFiled: October 21, 2005Date of Patent: October 7, 2008Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Angela T. Hui, Jean Yang, Yu Sun, Mark T. Ramsbey, Weidong Qian
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Publication number: 20080157187Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width.Type: ApplicationFiled: March 14, 2008Publication date: July 3, 2008Applicant: SPANSION LLCInventors: Weidong QIAN, Mark T. RAMSBEY, Tazrien KAMAL
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Patent number: 7307027Abstract: A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.Type: GrantFiled: August 11, 2005Date of Patent: December 11, 2007Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Minh Van Ngo, Alexander Nickel, Hieu Pham, Jean Yang, Hirokazu Tokuno, Weidong Qian
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Patent number: 7256141Abstract: A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.Type: GrantFiled: May 24, 2005Date of Patent: August 14, 2007Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Mark T. Ramsbey, Weidong Qian, Mark Chang, Eric Paton
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Patent number: 7232724Abstract: Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer.Type: GrantFiled: April 25, 2005Date of Patent: June 19, 2007Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Hidehiko Shiraiwa, Joong Jeon, Weidong Qian
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Publication number: 20070093042Abstract: A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.Type: ApplicationFiled: October 21, 2005Publication date: April 26, 2007Inventors: Angela Hui, Jean Yang, Yu Sun, Mark Ramsbey, Weidong Qian
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Publication number: 20070093070Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher Raeder, Christopher Foster, Weidong Qian, Minh Ngo
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Patent number: 7176113Abstract: The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.Type: GrantFiled: June 7, 2004Date of Patent: February 13, 2007Assignee: Spansion LLCInventors: Nga-Ching Alan Wong, Weidong Qian, Sameer Haddad, Mark Randolph, Mark Ramsbey, Tazrien Kamal
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Patent number: 7060564Abstract: A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.Type: GrantFiled: August 6, 2003Date of Patent: June 13, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Inkuk Kang, Hiroyuki Kinoshita, Weidong Qian, Kelwin King Wai Ko, Yu Sun
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Patent number: 7018868Abstract: The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.Type: GrantFiled: February 2, 2004Date of Patent: March 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Jean Y. Yang, Jeff P. Erhardt, Cyrus Tabery, Weidong Qian, Mark T. Ramsbey, Jaeyong Park, Tazrien Kamal
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Patent number: 6989320Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.Type: GrantFiled: May 11, 2004Date of Patent: January 24, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Weidong Qian, Mark Ramsbey, Jean Yee-Mei Yang, Sameer Haddad