Patents by Inventor Weifeng Ye
Weifeng Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250079239Abstract: Embodiments of the disclosure include a method of forming a gate-all-around (GAA) contact structure on a semiconductor substrate. The method will include removing material from surfaces of a feature formed in a surface of a substrate that includes a plurality of features that each include a plurality of source/drain contact surfaces, selectively forming a reaction product material over a surface of each of the plurality of source/drain contact surfaces, heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts, selectively forming a first metal layer on the surface of each of the plurality of contacts, selectively forming a second metal layer on the first metal layer, and filling the feature with a conductor material, wherein the conductor material comprises tungsten (W) or molybdenum (Mo).Type: ApplicationFiled: September 1, 2023Publication date: March 6, 2025Inventors: Jiang LU, Shumao ZHANG, Liqi WU, Yiyang WAN, Weifeng YE, Jianqiu GUO, Dong WANG, Qihao ZHU
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Publication number: 20250054812Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.Type: ApplicationFiled: December 29, 2023Publication date: February 13, 2025Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
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Publication number: 20250054767Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.Type: ApplicationFiled: April 25, 2024Publication date: February 13, 2025Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
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Publication number: 20240379768Abstract: Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.Type: ApplicationFiled: May 12, 2023Publication date: November 14, 2024Inventors: Shumao ZHANG, Le ZHANG, Weifeng YE, Chih-Hsun HSU, David T. OR, Gary HOW, Yiyang WAN, Liqi WU, Jiang LU
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Method of Selective Metal Deposition Using Separated Reactant Activation and Plasma Discharging Zone
Publication number: 20240191354Abstract: Methods of depositing a metal silicide on a substrate are provided herein. In some embodiments, a method of depositing a metal silicide on a substrate having a silicon containing surface includes: creating a plasma comprising a first gas in a plasma region in a chemical vapor deposition (CVD) chamber, wherein the plasma region is disposed between a lid heater and a showerhead; flowing the first gas through a plurality of first openings of the showerhead to an activation region in the CVD chamber disposed between the showerhead and the substrate; flowing a second gas comprising a metal precursor in a non-plasma state through a plurality of second openings of the showerhead to the activation region, wherein the plurality of second openings are fluidly independent from the plurality of first openings within the showerhead; mixing the first gas with the second gas to activate the second gas in the activation region; and exposing the silicon containing surface of the substrate to the activated second gas.Type: ApplicationFiled: December 9, 2022Publication date: June 13, 2024Inventors: Ying-Bing JIANG, Joung Joo LEE, Xianmin TANG, Jiang LU, Avgerinos V. GELATOS, Dien-yeh WU, Weifeng YE, Yiyang WAN, Gary HOW, Joseph HERNANDEZ -
Publication number: 20240105444Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.Type: ApplicationFiled: April 26, 2023Publication date: March 28, 2024Inventors: Jiang LU, Liqi WU, Wei DOU, Weifeng YE, Shih Chung CHEN, Rongjun WANG, Xianmin TANG, Yiyang WAN, Shumao ZHANG, Jianqiu GUO
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Publication number: 20230377892Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate comprises forming a plasma reaction between titanium tetrachloride (TlCl4), hydrogen (H2), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.Type: ApplicationFiled: May 19, 2022Publication date: November 23, 2023Inventors: Yiyang WAN, Weifeng YE, Shumao ZHANG, Gary HOW, Jiang LU, Lei ZHOU, Dien-yeh WU, Douglas LONG, Avgerinos V. GELATOS, Ying-Bing JIANG, Rongjun WANG, Xianmin TANG, Halbert CHONG
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Patent number: 10707122Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: GrantFiled: September 24, 2018Date of Patent: July 7, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Sree Rangasai V. Kesapragada, Kevin Moraes, Srinivas Guggilla, He Ren, Mehul Naik, David Thompson, Weifeng Ye, Yana Cheng, Yong Cao, Xianmin Tang, Paul F. Ma, Deenesh Padhi
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Patent number: 10546742Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.Type: GrantFiled: December 31, 2018Date of Patent: January 28, 2020Assignee: APPLIED MATERIALS, INC.Inventors: He Ren, Mehul B. Naik, Yong Cao, Yana Cheng, Weifeng Ye
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Publication number: 20190189433Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.Type: ApplicationFiled: December 31, 2018Publication date: June 20, 2019Inventors: He REN, Mehul B. NAIK, Yong CAO, Yana CHENG, Weifeng YE
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Publication number: 20190027403Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventors: Sree Rangasai V. KESAPRAGADA, Kevin MORAES, Srinivas GUGGILLA, He REN, Mehul NAIK, David THOMPSON, Weifeng YE, Yana CHENG, Yong CAO, Xianmin TANG, Paul F. MA, Deenesh PADHI
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Patent number: 10170299Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.Type: GrantFiled: June 18, 2016Date of Patent: January 1, 2019Assignee: Applied Materials, Inc.Inventors: He Ren, Mehul B. Naik, Yong Cao, Yana Cheng, Weifeng Ye
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Patent number: 10109520Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: GrantFiled: October 4, 2016Date of Patent: October 23, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Sree Rangasai V. Kesapragada, Kevin Moraes, Srinivas Guggilla, He Ren, Mehul Naik, David Thompson, Weifeng Ye, Yana Cheng, Yong Cao, Xianmin Tang, Paul F. Ma, Deenesh Padhi
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Patent number: 10043709Abstract: Methods for selectively depositing a cobalt layer are provided herein. In some embodiments, methods for selectively depositing a cobalt layer include: exposing a substrate to a first process gas to passivate an exposed dielectric surface, wherein the substrate comprises a dielectric layer having an exposed dielectric surface and a metal layer having an exposed metal surface; and selectively depositing a cobalt layer atop the exposed metal surface using a thermal deposition process.Type: GrantFiled: November 3, 2015Date of Patent: August 7, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Hua Ai, Jiang Lu, Avgerinos V. Gelatos, Paul F. Ma, Sang Ho Yu, Feng Q. Liu, Xinyu Fu, Weifeng Ye
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Publication number: 20180144973Abstract: Methods to selectively deposit capping layers on a copper surface relative to a dielectric surface comprising separately the copper surface to a cobalt precursor gas and a tungsten precursor gas, each in a separate processing chamber. The copper surface and the dielectric surfaces can be substantially coplanar. The combined thickness of cobalt and tungsten capping films is in the range of about 2 ? to about 60 ?.Type: ApplicationFiled: November 1, 2017Publication date: May 24, 2018Inventors: Weifeng Ye, Jiang Lu, Feng Chen, Zhiyuan Wu, Kai Wu, Vikash Banthia, He Ren, Sang Ho Yu, Mei Chang, Feiyue Ma, Yu Lei, Keyvan Kashefizadeh, Kevin Moraes, Paul F. Ma, Hua Ai
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Patent number: 9633861Abstract: Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer.Type: GrantFiled: February 13, 2014Date of Patent: April 25, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Weifeng Ye, Mei-yee Shek, Mihaela Balseanu, Xiaojun Zhang, Xiaolan Ba, Yu Jin, Li-Qun Xia
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Publication number: 20170098575Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: ApplicationFiled: October 4, 2016Publication date: April 6, 2017Inventors: Sree Rangasai V. KESAPRAGADA, Kevin MORAES, Srinivas GUGGILLA, He REN, Mehul NAIK, David THOMPSON, Weifeng YE, Yana CHENG, Yong CAO, Xianmin TANG, Paul F. MA, Deenesh PADHI
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Patent number: 9580801Abstract: Embodiments described herein generally relate to the formation of a UV compatible barrier stack. Methods described herein can include delivering a process gas to a substrate positioned in a process chamber. The process gas can be activated to form an activated process gas, the activated process gas forming a barrier layer on a surface of the substrate, the barrier layer comprising silicon, carbon and nitrogen. The activated process gas can then be purged from the process chamber. An activated nitrogen-containing gas can be delivered to the barrier layer, the activated nitrogen-containing gas having a N2:NH3 ratio of greater than about 1:1. The activated nitrogen-containing gas can then be purged from the process chamber. The above elements can be performed one or more times to deposit the barrier stack.Type: GrantFiled: November 7, 2014Date of Patent: February 28, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Xiaolan Ba, Weifeng Ye, Mei-yee Shek, Yu Jin, Li-Qun Xia, Deenesh Padhi, Alexandros T. Demos
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Publication number: 20170005041Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.Type: ApplicationFiled: June 18, 2016Publication date: January 5, 2017Inventors: He REN, Mehul B. NAIK, Yong CAO, Yana CHENG, Weifeng YE
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Patent number: 9478460Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. Embodiments described herein control selectivity of deposition by preventing damage to the dielectric surface, repairing damage to the dielectric surface, such as damage which can occur during the cobalt deposition process, and controlling deposition parameters for the cobalt layer.Type: GrantFiled: August 10, 2015Date of Patent: October 25, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Mei-yee Shek, Weifeng Ye, Li-Qun Xia, Kang Sub Yim, Kelvin Chan