Patents by Inventor Weifeng Ye
Weifeng Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12588443Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.Type: GrantFiled: April 26, 2023Date of Patent: March 24, 2026Assignee: Applied Materials Inc.Inventors: Jiang Lu, Liqi Wu, Wei Dou, Weifeng Ye, Shih Chung Chen, Rongjun Wang, Xianmin Tang, Yiyang Wan, Shumao Zhang, Jianqiu Guo
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Method of selective metal deposition using separated reactant activation and plasma discharging zone
Patent number: 12565702Abstract: Methods of depositing a metal silicide on a substrate are provided herein. In some embodiments, a method of depositing a metal silicide on a substrate having a silicon containing surface includes: creating a plasma comprising a first gas in a plasma region in a chemical vapor deposition (CVD) chamber, wherein the plasma region is disposed between a lid heater and a showerhead; flowing the first gas through a plurality of first openings of the showerhead to an activation region in the CVD chamber disposed between the showerhead and the substrate; flowing a second gas comprising a metal precursor in a non-plasma state through a plurality of second openings of the showerhead to the activation region, wherein the plurality of second openings are fluidly independent from the plurality of first openings within the showerhead; mixing the first gas with the second gas to activate the second gas in the activation region; and exposing the silicon containing surface of the substrate to the activated second gas.Type: GrantFiled: December 9, 2022Date of Patent: March 3, 2026Assignee: APPLIED MATERIALS, INC.Inventors: Ying-Bing Jiang, Joung Joo Lee, Xianmin Tang, Jiang Lu, Avgerinos V. Gelatos, Dien-yeh Wu, Weifeng Ye, Yiyang Wan, Gary How, Joseph Hernandez -
Patent number: 12538542Abstract: Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.Type: GrantFiled: May 12, 2023Date of Patent: January 27, 2026Assignee: Applied Materials, Inc.Inventors: Shumao Zhang, Le Zhang, Weifeng Ye, Chih-Hsun Hsu, David T. Or, Gary How, Yiyang Wan, Liqi Wu, Jiang Lu
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Publication number: 20250379031Abstract: Embodiments of the disclosure provide a method that includes delivering a pulsed radio frequency (RF) signal from a source RF generator to an electrode of a processing chamber. A plasma is formed in a processing region of the processing chamber based on the pulsed RF signal. The plasma is disposed between the electrode and a substrate. The pulsed RF signal is caused to have a duty cycle in a range of 5 to 15 percent. The pulsed RF signal is caused to have an off-time in a range of 50 to 250 microseconds. A first material is deposited on a second material of the substrate and a third material of the substrate based on the duty cycle and the off-time.Type: ApplicationFiled: May 21, 2025Publication date: December 11, 2025Inventors: Yiyang WAN, Yunho KIM, Shumao ZHANG, Chih-Hsun HSU, Weifeng YE, Jiang LU
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Publication number: 20250376762Abstract: Embodiments of the present principles generally relate to forming low resistivity contacts for semiconductor device formation. In some embodiments, a method of forming a metal silicide layer on a surface of a contact structure includes depositing a first layer including a metal on a first surface that includes silicon and a second surface that includes a dielectric material by providing a carrier gas, a metal-containing precursor, and a hydrogen-containing precursor to a deposition chamber and applying an RF power while maintaining the substrate at a first temperature. The method includes delivering a gas mixture including titanium tetrachloride (TiCl4) to the first surface and the second surface, while maintaining the substrate at the first temperature, to remove at least a portion of the deposited metal and cyclically repeating the metal deposition and the delivering the gas mixture processes to reach the desired thickness of the metal silicide layer.Type: ApplicationFiled: May 14, 2025Publication date: December 11, 2025Inventors: Yiyang WAN, Shumao ZHANG, Chih-Hsun HSU, Weifeng YE, Wei ZHANG, Jiang LU
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Publication number: 20250372449Abstract: The present disclosure generally provides methods of forming contact structures on semiconductor substrates. The method includes forming a titanium layer on a surface of the contact structure. The contact structure includes a feature formed in a surface of the semiconductor substrate. The feature includes an opening that is defined by a silicon containing contact, a bottom surface, and sidewalls, which comprise a dielectric material. The titanium layer is at least formed over the sidewalls and the silicon containing contact. A first selective capping layer is formed. The first selective capping layer is formed over the titanium layer. A second selective capping layer is formed. The second selective capping layer is formed over the silicon containing contact, where at least a portion of the formed titanium layer is disposed between the second selective capping layer and the surface of the silicon containing contact.Type: ApplicationFiled: January 3, 2025Publication date: December 4, 2025Inventors: Yiyang WAN, Weifeng YE, Le ZHANG, Yiyang LU, Chih-Hsun HSU, Qihao ZHU, Jiang LU
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Publication number: 20250372450Abstract: The present disclosure generally provides methods of forming contact structures on semiconductor substrates. The methods include forming a first metal containing layer on a surface of the contact structure and forming a second metal containing layer over the first metal containing layer. Performing a gradient etch process including exposing the first metal containing layer and the second metal containing layer to an etchant gas containing plasma to remove at least a portion of the first metal containing layer and the second metal containing layer from the sidewalls. Performing a selective etch process including a deposition operation, an etch operation and a trim operation. Performing a post etch treatment process including exposing the first metal containing layer and a carbon-containing passivation layer with a hydrogen plasma to remove at least a portion of the carbon-containing passivation layer.Type: ApplicationFiled: January 3, 2025Publication date: December 4, 2025Inventors: Le ZHANG, Yiyang LU, Yiyang WAN, Chih-Hsun HSU, Weifeng YE, Shumao ZHANG, Wei ZHANG, Qihao ZHU, Liqi WU, Jiang LU
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Publication number: 20250372448Abstract: The present disclosure generally provides methods of forming contact structures on semiconductor substrates. The methods include forming a metal silicide layer on a surface of a contact structure by maintaining a first temperature of a substrate and providing a first carrier gas, a first metal-containing precursor, and a first hydrogen-containing precursor to a first deposition chamber. The contact structure includes a feature formed in a surface of the semiconductor substrate. The metal silicide layer is formed over the sidewalls and the silicon containing contact. The metal silicide layer is exposed to a chlorine containing plasma to remove at least a portion of the metal silicide layer formed on the sidewalls. A metal layer is formed on a surface of the silicon containing contact. A portion of the formed metal silicide layer is disposed between the metal layer and the surface of the silicon containing contact.Type: ApplicationFiled: January 3, 2025Publication date: December 4, 2025Inventors: Yiyang WAN, Le ZHANG, Chih-Hsun HSU, Weifeng YE, Shumao ZHANG, Wei ZHANG, Qihao ZHU, Yiyang LU, Liqi WU, Jiang LU
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Publication number: 20250174456Abstract: Methods of depositing titanium silicide (TiSi) in the formation of semiconductor structures are described. The methods include thermal chemical vapor deposition (CVD) in which a semiconductor substrate in a semiconductor processing chamber is exposed to a titanium-containing precursor, a silicon-containing precursor, and hydrogen (H2) to deposit the titanium silicide (TiSi) layer directly on the semiconductor substrate. Methods of selectively depositing titanium silicide (TiSi) in the formation of semiconductor structures, e.g., an n-type transistor and a p-type transistor, are also described.Type: ApplicationFiled: November 24, 2023Publication date: May 29, 2025Applicant: Applied Materials, Inc.Inventors: Shumao Zhang, Qihao Zhu, Weifeng Ye, Liqi Wu, Jiang Lu
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Publication number: 20250112091Abstract: A contact structure includes a cavity comprising a device contact formed on a surface of a substrate, a bottom surface, and sidewalls. A metal silicide layer disposed over the surface of the device contact, the bottom surface, and the sidewalls of the cavity, and a treated surface formed over a portion of the metal silicide layer disposed over the sidewalls of the cavity.Type: ApplicationFiled: September 27, 2024Publication date: April 3, 2025Inventors: Jianqiu GUO, Dong WANG, Liqi WU, Yiyang WAN, Shumao ZHANG, Qihao ZHU, Weifeng YE, Jiang LU, Shihchung CHEN
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Publication number: 20250079239Abstract: Embodiments of the disclosure include a method of forming a gate-all-around (GAA) contact structure on a semiconductor substrate. The method will include removing material from surfaces of a feature formed in a surface of a substrate that includes a plurality of features that each include a plurality of source/drain contact surfaces, selectively forming a reaction product material over a surface of each of the plurality of source/drain contact surfaces, heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts, selectively forming a first metal layer on the surface of each of the plurality of contacts, selectively forming a second metal layer on the first metal layer, and filling the feature with a conductor material, wherein the conductor material comprises tungsten (W) or molybdenum (Mo).Type: ApplicationFiled: September 1, 2023Publication date: March 6, 2025Inventors: Jiang LU, Shumao ZHANG, Liqi WU, Yiyang WAN, Weifeng YE, Jianqiu GUO, Dong WANG, Qihao ZHU
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Publication number: 20250054812Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.Type: ApplicationFiled: December 29, 2023Publication date: February 13, 2025Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
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Publication number: 20250054767Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.Type: ApplicationFiled: April 25, 2024Publication date: February 13, 2025Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
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Publication number: 20240379768Abstract: Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.Type: ApplicationFiled: May 12, 2023Publication date: November 14, 2024Inventors: Shumao ZHANG, Le ZHANG, Weifeng YE, Chih-Hsun HSU, David T. OR, Gary HOW, Yiyang WAN, Liqi WU, Jiang LU
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Method of Selective Metal Deposition Using Separated Reactant Activation and Plasma Discharging Zone
Publication number: 20240191354Abstract: Methods of depositing a metal silicide on a substrate are provided herein. In some embodiments, a method of depositing a metal silicide on a substrate having a silicon containing surface includes: creating a plasma comprising a first gas in a plasma region in a chemical vapor deposition (CVD) chamber, wherein the plasma region is disposed between a lid heater and a showerhead; flowing the first gas through a plurality of first openings of the showerhead to an activation region in the CVD chamber disposed between the showerhead and the substrate; flowing a second gas comprising a metal precursor in a non-plasma state through a plurality of second openings of the showerhead to the activation region, wherein the plurality of second openings are fluidly independent from the plurality of first openings within the showerhead; mixing the first gas with the second gas to activate the second gas in the activation region; and exposing the silicon containing surface of the substrate to the activated second gas.Type: ApplicationFiled: December 9, 2022Publication date: June 13, 2024Inventors: Ying-Bing JIANG, Joung Joo LEE, Xianmin TANG, Jiang LU, Avgerinos V. GELATOS, Dien-yeh WU, Weifeng YE, Yiyang WAN, Gary HOW, Joseph HERNANDEZ -
Publication number: 20240105444Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.Type: ApplicationFiled: April 26, 2023Publication date: March 28, 2024Inventors: Jiang LU, Liqi WU, Wei DOU, Weifeng YE, Shih Chung CHEN, Rongjun WANG, Xianmin TANG, Yiyang WAN, Shumao ZHANG, Jianqiu GUO
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Publication number: 20230377892Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate comprises forming a plasma reaction between titanium tetrachloride (TlCl4), hydrogen (H2), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.Type: ApplicationFiled: May 19, 2022Publication date: November 23, 2023Inventors: Yiyang WAN, Weifeng YE, Shumao ZHANG, Gary HOW, Jiang LU, Lei ZHOU, Dien-yeh WU, Douglas LONG, Avgerinos V. GELATOS, Ying-Bing JIANG, Rongjun WANG, Xianmin TANG, Halbert CHONG
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Patent number: 10707122Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.Type: GrantFiled: September 24, 2018Date of Patent: July 7, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Sree Rangasai V. Kesapragada, Kevin Moraes, Srinivas Guggilla, He Ren, Mehul Naik, David Thompson, Weifeng Ye, Yana Cheng, Yong Cao, Xianmin Tang, Paul F. Ma, Deenesh Padhi
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Patent number: 10546742Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.Type: GrantFiled: December 31, 2018Date of Patent: January 28, 2020Assignee: APPLIED MATERIALS, INC.Inventors: He Ren, Mehul B. Naik, Yong Cao, Yana Cheng, Weifeng Ye
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Publication number: 20190189433Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.Type: ApplicationFiled: December 31, 2018Publication date: June 20, 2019Inventors: He REN, Mehul B. NAIK, Yong CAO, Yana CHENG, Weifeng YE