Abstract: Disclosed herein is a 2K clearcoat coating composition including (A) from 10% to 70% by weight of a first resin having at least one primary hydroxyl group; (B) from 2% to 40% by weight of a second resin including a resin (B-1) having at least one primary hydroxyl group and/or a resin (B-2) having at least one secondary hydroxyl group; and (C) a crosslinker including at least one polyisocyanate and at least one amino resin, and the weight percentages of components (A) and (B) are based on the total weight of the coating composition and the ratio by weight between components (A) and (B) is in a range of from 6:1 to 1:2. Further disclosed herein is an article coated by the coating composition and the article may have metal substrates.

Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.

Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.

Abstract: A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.

Abstract: The present invention provides fluorogenic substrates and methods of use in detecting and analyzing phospholipase C isozyme (PLC) activity.

Abstract: The present invention provides fluorogenic substrates and methods of use in detecting and analyzing phospholipase C isozyme (PLC) activity.

Abstract: An abrasive article comprising a backing material having first and second opposed major surfaces and an abrasive layer comprising abrasive particles and binder secured to the said first major surface, the article also bearing a hydrophilic/lipophilic urethane material to enhance dimensional and conformational stability of the abrasive article.