Patents by Inventor Wei Gang Huang

Wei Gang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063720
    Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yen-Chieh Huang, Wei-Gang Chiu, Kai-Wen Cheng, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250031388
    Abstract: A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 23, 2025
    Inventors: I-Che Lee, Pin-Ju Chen, Wei-Gang Chiu, Yen-Chieh Huang, Kai-Wen Cheng, Huai-Ying Huang, Yu-Ming Lin
  • Patent number: 8703437
    Abstract: The present invention provides fluorogenic substrates and methods of use in detecting and analyzing phospholipase C isozyme (PLC) activity.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: April 22, 2014
    Assignee: The University of North Carolina at Chapel Hill
    Inventors: Qisheng Zhang, Wei Gang Huang, John Sondek, Stephanie Hicks
  • Publication number: 20130183701
    Abstract: The present invention provides fluorogenic substrates and methods of use in detecting and analyzing phospholipase C isozyme (PLC) activity.
    Type: Application
    Filed: June 7, 2011
    Publication date: July 18, 2013
    Inventors: Qisheng Zhang, Wei Gang Huang, John Sondek, Stephanie Hicks
  • Publication number: 20030166387
    Abstract: An abrasive article comprising a backing material having first and second opposed major surfaces and an abrasive layer comprising abrasive particles and binder secured to the said first major surface, the article also bearing a hydrophilic/lipophilic urethane material to enhance dimensional and conformational stability of the abrasive article.
    Type: Application
    Filed: January 15, 2003
    Publication date: September 4, 2003
    Applicant: 3M Innovative Properties Company
    Inventors: Pei-Jung Chen, Robert F. Smith, Wei Gang Huang