Abstract: A digital-to-analog converter (DAC) includes a plurality of DAC cells, a mismatch error sorting circuit, and a dynamic element matching (DEM) circuit. The mismatch error sorting circuit generates a sorting result of the plurality of DAC cells according to mismatch error levels of the plurality of DAC cells. The DEM circuit shapes the mismatch error levels of the plurality of DAC cells according to the sorting result of the plurality of DAC cells.

Abstract: Reinforcement components for electrical connections with limited accessibility Shield structures with reduced spacing between adjacent insulation components and systems and methods for making the same are provided. In some embodiments, a reinforcement component may be compressed between two portions of a first electronic component in order to deform the reinforcement component for filling in a void between the reinforcement component and a coupling formed between the first electronic component and a second electronic component. The first electronic component may be a flexible circuit component that may be folded over the reinforcement component prior to the reinforcement component being compressed. This may enable the reinforcement component to be effectively positioned with respect to the first electronic component prior to being deformed for reinforcing one or more couplings made between the first electronic component and the second electronic component.

Abstract: A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

Abstract: A panel module is provided, including a first substrate, a second substrate, a first optical glue, and a second optical glue. The first and second optical glues are disposed between the first and second substrates, wherein the first optical glue protrudes from the first substrate, and the second optical glue adheres the first substrate to the second substrate. Specifically, the viscosity of the second optical glue is smaller than the first optical glue before solidification.

Abstract: A touch panel display is provided. The display includes a display module and a transparent top plate disposed above the display module. The transparent top plate has a touch surface opposite to the display module. A spacer is disposed between the display module and the transparent top plate to form a first cavity therebetween. The spacer includes a first adhesive film attached to the display module, a second adhesive film attached to the transparent top plate and a hard transparent layer sandwiched between the first and second adhesive films. An assembly process and a touch sensing module thereof are also disclosed.

Abstract: A panel module is provided, including a first substrate, a second substrate, a first optical glue, and a second optical glue. The first and second optical glues are disposed between the first and second substrates, wherein the first optical glue protrudes from the first substrate, and the second optical glue adheres the first substrate to the second substrate. Specifically, the viscosity of the second optical glue is smaller than the first optical glue before solidification.

Abstract: A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

Abstract: A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

Abstract: A connection structure for a chip-on-glass (COG) driver IC and a connection method therefor are provided. The connection structure includes a driver IC having a surface provided with a plurality of polymeric bumps and a plurality of conductive bumps, and the height of the polymeric bumps in relation to the surface is smaller than that of the conductive bumps. When the driver IC is bonded to a glass substrate via an adhesive film by thermal compression bonding, the polymeric bumps are embedded into the adhesive film, and a gap is defined between the polymeric bumps and the glass substrate. Thus, the polymeric bumps can increase the contact area between the driver IC and the adhesive film, and enhance the connection reliability between the conductive bumps and pads of the glass substrate.

Abstract: The present invention discloses a bump structure and a method for fabricating the same. The bump structure of the present invention comprises a semiconductor substrate having a plurality of connection pads; a passivation layer covering the substrate and having openings each corresponding to one connection pad, wherein the openings reveal a portion of each connection pad to form a plurality of electrical-connection areas; an elastic layer formed on the passivation layer; and a plurality of bumps each formed corresponding to one electric-connection area and extending to the elastic layer, whereby the elasticity and deformability of the bumps is enhanced. The present invention uses a larger-texture (?20 ?m) patterning process to fabricate an appropriate patterned elastic layer (having parallel lines, strips, or saw teeth) to enhance the elasticity and deformability of the bumps, whereby the bump structure of the present invention can apply to a fine-pitch IC.

Abstract: A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

Abstract: An electronic structural member or a semiconductor device having conductive bumps is provided. The conductive bump includes an organic buffer layer with an undercut structure, and the conductive bump is deformable during the bonding process so as to compensate the height difference between the conductive bumps. In addition, an adhesive is further disposed between the IC chip and the substrate, and partial adhesive fills in the undercut structure, such that not only the adhesive area can be increased to enhance the bonding force between the IC chip and the substrate, but the return force of the adhesive can be reduced.