Abstract: Embodiments of the present disclosure provide a method for recommending a podcast in music application and a device, where the method includes: a terminal device receives a start instruction for a podcast interface the music application; and the terminal device displays a first preset number of recommended podcast programs in the podcast interface in response to the start instruction, where each of the recommended podcast programs is an episode of audio data, and the recommended podcast programs include a podcast program matching with a preference of a user who uses the music application.

Abstract: The present application relates to a method for statistical distribution characterization of dendritic structures in original position of single crystal superalloy, and relates to the technical field of analysis of metal material composition and microstructure, comprising the following steps: step 1, processing a to-be-tested sample and determining a calibration coefficient; step 2, obtaining a two-dimensional element content distribution map of the to-be-tested sample; and step 3, determining the number and average spacing of primary dendrites. A composition distribution region analyzed in the present application is larger than the area of a distribution region of the traditional microscopic analysis method, and the sample preparation is simple. The distribution, number and average spacing of the primary dendrites can be obtained without metallographic corrosion sampling.

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: The present disclosure discloses a three-dimensional stacked package structure with a micro-channel heat dissipation structure and a packaging method thereof. The three-dimensional stacked package structure includes a chip package portion comprising a multi-layered structure with stacked chips, wherein the stacked chips are provided with through silicon vias and packaged in a three-dimensional stacked packaging manner and a silicon substrate package portion comprising a silicon substrate. The silicon substrate is provided with micro bumps which are to be interconnected with external lead wires. The chip package portion is assembled on the silicon substrate by bonding with the micro bumps. The stacked chips are etched with micro-channels and through holes corresponding to each other. The micro-channels are for coolant flowing in a horizontal direction, and the through holes are for coolant flowing in upper and lower layers. Sealing rings are arranged around the micro-channels and the through holes.

Abstract: Systems (100, 900, 1100), devices, and methods may be used to print or use a patient-specific waterjet cut guide (104, 302, 902, 1102). A method may include receiving, at a processor, image data of a bone (102, 308) of a patient (702), rendering a model of the bone (102, 308) (704) and generating a cut guide model using the model of the bone (102, 308) (706). The method may include printing, using a three-dimensional (3D) printer, a waterjet cut guide (104, 302, 902, 1102) using the cut guide model. A method may include using the patient-specific waterjet cut guide (104, 302, 902, 1102) to perform a resection using a waterjet cutting device, the waterjet cutting device including a nozzle (108, 306, 406, 500A, 500B) insertable into a cut guide slot (106B, 304, 310, 906, 1104) of the patient-specific waterjet cut guide (104, 302, 902, 1102).

Abstract: Embodiments of the present disclosure provide a method for recommending a podcast in music application and a device, where the method includes: a terminal device receives a start instruction for a podcast interface the music application; and the terminal device displays a first preset number of recommended podcast programs in the podcast interface in response to the start instruction, where each of the recommended podcast programs is an episode of audio data, and the recommended podcast programs include a podcast program matching with a preference of a user who uses the music application.

Abstract: A method and an apparatus for real-time data analysis of water pipe network are proposed. The method includes: step S1: obtaining a current flow data xi to be identified, where i is a positive integer greater than or equal to 2; step S2: determining whether a first difference between the current flow data xi to be identified and a previous identified flow data xi?1 adjacent to the current flow data xi to be identified is less than or equal to a preset threshold; step S3: determining whether a second difference between a next to-be-identified flow data xi+1 adjacent to the current flow data xi to be identified and the previous identified flow data xi?1 is less than or equal to the preset threshold in response to the first difference being greater than the preset threshold.

Abstract: Apparatuses and techniques are described for performing an operation which irreversibly prevents access to a set of memory cells. The operation provides a strong erase bias for select gate transistors of NAND strings. The erase bias induces a phenomenon in the select gate transistors which permanently increases their threshold voltages. This prevents access to the memory cells such as for program or read operations. The operation can involve one or more erase-verify iterations. In each erase-verify iteration, an erase bias is applied to the select gate transistors such as by charging up the channels of the NAND strings and holding a control gate voltage of the select gate transistors at a relatively low level, thereby causing a relatively high channel-to-control gate voltage.

Abstract: A method and an apparatus for real-time data analysis of water pipe network are proposed. The method includes: step S1: obtaining a current flow data xi to be identified, where i is a positive integer greater than or equal to 2; step S2: determining whether a first difference between the current flow data xi to be identified and a previous identified flow data xi?1 adjacent to the current flow data xi to be identified is less than or equal to a preset threshold; step S3: determining whether a second difference between a next to-be-identified flow data xi+1 adjacent to the current flow data xi to be identified and the previous identified flow data xi?1 is less than or equal to the preset threshold in response to the first difference being greater than the preset threshold.