Abstract: This disclosure is directed to a liquid cooling device having at least two collecting tanks and at least one pair of heat-exchange plates. The tanks are separated from each other. Each of the collecting tanks has a joint tube. Each of the heat-exchange plates is in elongated shape and the collecting tanks are connected serially by the heat-exchange plates. The two collecting tanks are connected by the pair of heat-exchange plates. Each of the heat-exchange plates has a channel extended along the longitudinal direction thereof. The channels in the heat-exchange plates are connected to the collecting tanks at two ends of the heat-exchange plates, respectively. The longitudinal directions of the channels of the heat-exchange plates between the collecting tanks are parallel to each other.

Abstract: A data transmission system and method thereof for edge computing are provided. A terminal mobile station international subscriber directory number (MSISDN) and a terminal IP of a target terminal are obtained with a domain name system (DNS) by a device providing communication services from the data transmission system. After data packets are sent to the data transmission system, if the target terminal is in an idle mode, a paging message is sent by a terminal wake-up module to enable the target terminal to return to a connected mode for communication. Before a connection is established between the data transmission system and the target terminal, downlink data packets can be temporarily stored, and the packets can be sent after the target terminal is in the connected mode. A computer readable medium for executing the data transmission method is also provided.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.

Abstract: The present disclosure provides a method for anti-tampering apparatus servicing data implemented by a calculation device connected to a target device, the method comprising: identifying a contract identification code and obtaining a contract package file and a contract authentication code from at least one remote device; obtaining a microservice file corresponding to the target device from the remote device when a device embedded code of the calculation device is matching the contract authentication code; performing the microservice file to enable the target device according to the contract package file and generate an execution report; publishing the execution report to the remote device to obtain an acceptance certification code; and combining and hashing the device embedded code, the contract authentication code and the acceptance certification code to generate a hash value, and sending the hash value to a blockchain.

Abstract: The invention provides a power supply including at least one power output port, at least one status alert component, and at least one output port status monitoring module. The status alert component generates at least one visual prompt based on an alert signal. The output port status monitoring module includes at least one temperature sensor adjacent to the power output port, a microcontroller connected to the temperature sensor and sensing an output current from the power output port, and a reset signal generator connected to the microcontroller. The microcontroller comprises at least one port status alert condition that takes a temperature and the output current of the power output port as decision factors. The microcontroller outputs the alert signal to the status alert component when the port status alert condition is met and maintains the status until a reset signal provided by the reset signal generator is received.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.

Abstract: An anti-peep display device includes a display module and an anti-peep module disposed on the display module. The anti-peep module includes the following features. The first light incident surface faces the display surface, the second and third light incident surfaces are located on opposite sides of the first light incident surface, the first condensing portion is disposed corresponding to the second light incident surface and the first light source, the second condensing portion is disposed corresponding to the third light incident surface and the second light source, the first and second condensing portions convert beams of the first and second light sources into anti-peep beams with a beam angle less than 10 degrees, and the optical microstructures reflect the anti-peep beams and exit the anti-peep beams from the light guide plate. The present invention also provides an anti-peep method applicable to the anti-peep display device.

Abstract: Embodiments of the present disclosure relates to a method for forming a semiconductor device structure. The method includes including forming one or more conductive features in a first interlayer dielectric (ILD), forming an etch stop layer on the first ILD, forming a second ILD over the etch stop layer, forming one or more openings through the second ILD and the etch stop layer to expose a top surface of the one or more first conductive features, wherein the one or more openings are formed by a first etch process in a first process chamber, exposing the one or more openings to a second etch process in a second process chamber so that the shape of the or more openings is elongated, and filling the one or more openings with a conductive material.

Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: A test device includes a power compensation module and a test module. The power compensation module receives AC power generated by a device under test to generate DC power to the device under test. The test module provides a plurality of test signals and a test mode to the device under test for testing the device under test.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A semiconductor device includes a first device formed over a substrate. The first device includes a first device formed over a substrate, and the first device includes a first gate stack structure encircling a plurality of first nanostructures. The semiconductor device includes a first epitaxy structure wrapping an end of one of the first nanostructures, and a second device formed over the first device, wherein the second device includes a second gate stack structure encircling a plurality of second nanostructures. The semiconductor device includes a second epitaxy structure wrapping an end of one of the second nanostructures, and the second epitaxy structure is directly above the first epitaxy structure.