Abstract: A printed circuit board, which comprises a substrate, a conductive pattern disposed on a surface of said substrate and a solder mask coated on the surface of said substrate and covered over the conductive pattern. The conductive pattern has a bonding pad. The solder mask has an opening corresponding in location to the bonding pad such that a portion of the bonding pad is exposed outside. A space is left between said solder mask and said bonding pad and is communicated with the opening. Whereby, a solder ball can be received in the opening and the space and electrically connected to the bonding pad, such that the solder ball is held on the printed circuit board securely.

Abstract: A mold structure for package fabrication is proposed, and includes a top mold, a fixture and a bottom mold. The top mold is formed with at least an upwardly recessed portion; the fixture is formed with a plurality of downwardly recessed portions; and the bottom mold has a recessed cavity for receiving the fixture therein, and adapted to be engaged with the top mold, wherein a resilient member is disposed on an inner wall of the recessed cavity, and interposed between the fixture and the recessed cavity of the bottom mold, allowing the resilient member to provide a resilient force for properly positioning the fixture. By using the above mold structure, chips mounted on a substrate can be firmly supported in the mold structure without causing chip cracks during a molding process for encapsulating the chips.

Abstract: The present invention is to provide a double-sided thermally enhanced IC chip package which includes a chip being received in an opening of a substrate and electrically connected to a conductive circuit pattern on a top surface of the substrate through bonding wires. A thermally and electrically conductive planar member is attached to an inactive side of the chip through a thermally and electrically conductive adhesive layer. A portion of an active side of the chip to which the bonding wires are connected is encapsulated by a dielectric encapsulant, and the other portion of the active side of the chip is covered by a thermally and electrically conductive encapsulant. Thus, heat generated by the chip can be efficiently dissipated through the planar member and the thermally and electrically conductive encapsulant. The present invention also discloses a stacked chip package with double-sided heat dissipation capability.

Abstract: A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.

Abstract: The present invention is to provide a double-sided thermally enhanced IC chip package which includes a chip being received in an opening of a substrate and electrically connected to a conductive circuit pattern on a top surface of the substrate through bonding wires. A thermally and electrically conductive planar member is attached to an inactive side of the chip through a thermally and electrically conductive adhesive layer. A portion of an active side of the chip to which the bonding wires are connected is encapsulated by a dielectric encapsulant, and the other portion of the active side of the chip is covered by a thermally and electrically conductive encapsulant. Thus, heat generated by the chip can be efficiently dissipated through the planar member and the thermally and electrically conductive encapsulant. The present invention also discloses a stacked chip package with double-sided heat dissipation capability.

Abstract: The present invention is to provide a printed circuit board, which comprises a substrate, a conductive pattern disposed on a surface of said substrate and a solder mask coated on the surface of said substrate and covered over the conductive pattern. The conductive pattern has a bonding pad. The solder mask has an opening corresponding in location to the bonding pad such that a portion of the bonding pad is exposed outside. A space is left between said solder mask and said bonding pad and is communicated with the opening. Whereby, a solder ball can be received in the opening and the space and electrically connected to the bonding pad, such that the solder ball is held on the printed circuit board securely.

Abstract: A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.

Abstract: A strengthened bonding mechanism for a semiconductor package is proposed. An aluminum pad formed on a chip is formed with a UBM (under bump metallurgy) structure, on which a tin layer is applied. Moreover, a copper pad formed on a substrate or printed circuit board is formed with a tin layer thereon. Thereby, a solder ball or bump is adapted to be bonded to the tin layer for electrical connection purpose. With provision of the tin layer, the solder ball or bump would be strongly bonded to the bonding mechanism without being easily subject to breaking or cracking, thereby making reliability of fabricated products firmly assured. As such, bonding mechanisms can be densely arrangement so as to reduce pitch spacing between adjacent solder balls or bumps bonded to the bonding mechanisms, in favor of fine-pitch structural arrangement for facilitating electrical connection efficiency.

Abstract: A mold structure for package fabrication is proposed, and includes a top mold, a fixture and a bottom mold. The top mold is formed with at least an upwardly recessed portion; the fixture is formed with a plurality of downwardly recessed portions; and the bottom mold has a recessed cavity for receiving the fixture therein, and adapted to be engaged with the top mold, wherein a resilient member is disposed on an inner wall of the recessed cavity, and interposed between the fixture and the recessed cavity of the bottom mold, allowing the resilient member to provide a resilient force for properly positioning the fixture. By using the above mold structure, chips mounted on a substrate can be firmly supported in the mold structure without causing chip cracks during a molding process for encapsulating the chips.

Abstract: A wire-bonded chip on board package has a substrate including a first resin. A solder mask made of a second resin having a thermal expansion coefficient identical to that of the first resin of the substrate is disposed on the top surface of the substrate such that it has a smooth outer surface and some openings to expose the respective areas of the conductive patterns on the top surface. An IC chip with an inactive side thereof tightly attaches to the outer surface of the solder mask. Wire bonds electrically connect the contact pads formed on an active side of the IC chip to the conductive patterns of the top surface. A molding material encapsulates the chip, the wire bonds and the substrate top surface.

Abstract: A flip chip package has a substrate made of a material including an epoxy resin. A solder mask is one layer of an epoxy resin disposed on the top surface of the substrate. The solder mask has a smooth outer surface and a plurality of opening to expose the conductive patterns formed on the top surface. An IC chip includes an active side having a plurality of electrical contact pads. A plurality of solder bumps, each bump is formed on a respective one of the plurality of contact pads on the IC chip. The active side of the IC chip is tightly attached to the outer surface of the solder mask such that after a soldering process each said bump has a remainder completely received in a respective one of the opening of the solder mask and connected to the conductive patterns therein.

Abstract: A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: A low profile stack semiconductor package is proposed, wherein at least two chips having centrally-situated bond pads are stacked on a substrate that is formed with a through opening. A first chip is mounted on the substrate, with bond pads thereof being exposed to the opening. A second chip mounted on the first chip, is formed with a peripherally-situated cushion member, whereby bonding wires are adapted to extend from bond pads of the second chip in a direction parallel to the chip, and reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate, wherein the bonding wires are free of forming wire loops as extending above the second chip. By the above structure, the bonding wires would be firmly held in position to be free of contact or short circuit with the second chip, and overall package profile can be significantly miniaturized.