Patents by Inventor Weihong GAO

Weihong GAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10649026
    Abstract: A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Oliver D. Patterson, Peter Lin, Weihong Gao
  • Patent number: 10234500
    Abstract: A method and apparatus for separating real DVC via defects from nuisance based on Net Tracing Classification of eBeam VC die comparison inspection results are provided. Embodiments include performing an eBeam VC die comparison inspection on each via of a plurality of dies; determining DVC vias based on the comparison; performing a Net Tracing Classification on the DVC vias; determining S/D DVC vias based on the Net Tracing Classification; and performing a die repeater analysis on the S/D DVC vias to determine systematic design-related DVC via defects.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Weihong Gao, Xuefeng Zeng, Yan Pan, Peter Lin, Hoang Nguyen, Ho Young Song
  • Publication number: 20180284184
    Abstract: A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: OLIVER D. PATTERSON, PETER LIN, WEIHONG GAO
  • Publication number: 20160306009
    Abstract: A method and apparatus for separating real DVC via defects from nuisance based on Net Tracing Classification of eBeam VC die comparison inspection results are provided. Embodiments include performing an eBeam VC die comparison inspection on each via of a plurality of dies; determining DVC vias based on the comparison; performing a Net Tracing Classification on the DVC vias; determining S/D DVC vias based on the Net Tracing Classification; and performing a die repeater analysis on the S/D DVC vias to determine systematic design-related DVC via defects.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 20, 2016
    Inventors: Weihong GAO, Xuefeng ZENG, Yan PAN, Peter LIN, Hoang NGUYEN, Ho Young SONG