Abstract: An electronic package structure includes a lower circuit pattern structure, an upper circuit pattern structure, a reflowable material and at least one core element. The upper circuit pattern structure is disposed above the lower circuit pattern structure. The reflowable material is disposed between the upper circuit pattern structure and the lower circuit pattern structure. The core element attaches to the reflowable material and is configured to inhibit displacement of the at least one core element during a reflow process.

Abstract: An object classification model training method, a computation device for training an object classification model, an object recognition device, and an object recognition method are provided. The object classification model training method comprises steps of: receiving multiple model files each respectively having a virtual object 3D model; generating multiple 2D images of each virtual object 3D model by a revolving image-capture schedule, wherein the positions of the virtual object 3D model in the multiple 2D images are different; generating a training data set for each virtual object 3D model based on the multiple 2D images of each virtual object 3D model; and training an untrained model according to the training data sets corresponding to the virtual object 3D models of the multiple model files to obtain an object classification model.

Abstract: An isolation pattern module for manufacturing an isolation pattern includes a first sub-isolation-pattern and a second sub-isolation-pattern. The sub-isolation-pattern includes a plurality of pattern units, and each of the pattern units has a pitch boundary to define a closed area. The second sub-isolation-pattern corresponds to the pitch boundary of each of the pattern units and overlaps the closed area.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A laser detector includes a delay chain circuit and a warning circuit. The warning circuit is coupled to the delay chain circuit for generating a warning signal. The delay chain circuit includes N inverters coupled in series, an input terminal configured to receive an input voltage to the N inverters, and an output terminal configured to output an output voltage generated by the N inverters. N is a positive integer.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3?D3?S, L4?D4?S, and D3?D4.

Abstract: An electronic structure includes a packaging structure, a circuit pattern structure, an underfill and a protrusion structure. The circuit pattern structure is disposed over the packaging structure. A gap is between the circuit pattern structure and the packaging structure. The underfill is disposed in the gap. The protrusion structure is disposed in the gap, and is configured to facilitate the distributing of the underfill in the gap.

Abstract: An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: A package structure is provided. The package structure includes a substrate, a first electronic component, a first electrical connector, and a protective layer. The first electronic component is over the substrate. The first electrical connector is between the substrate and the first electronic component. The protective layer encapsulates the first electrical connector. The protective layer has a first curved lateral surface concave toward the first electrical connector and recessed with respect to a lateral surface of the first electronic component.

Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.

Abstract: A method for manufacturing an electronic device is provided. In the method for manufacturing an electronic device, a substrate is provided, a device layer is disposed on the substrate, and a photoresist layer is disposed on the device layer. Next, a photo mask is disposed on the photoresist layer, and a light source is used to firstly illuminate the photo mask to form a first exposure region. After that, a relative movement is made between the substrate and the photo mask, and the light source is used to secondly illuminate the photo mask to form a second exposure region, wherein the first exposure region partially overlaps the second exposure region. Afterwards, a pattern is developed on the substrate, the device layer is etched using a patterned photoresist layer as an etching mask, and then the patterned photoresist layer is removed.

Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3?D3?S, L4?D4?S, and D3?D4.

Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: A method of deploying microservice includes: determining whether a current load of a task queue of a target edge host is not smaller than a load alert level; if the current load is not smaller than the load alert level, calculating a task migration number of a first queue of the task queue to deploy a microservice corresponding to the first queue at at least one of a first available edge host and a cloud host; if the current load is smaller than the load alert level, calculating a long-term load according to a history pushing rate, a history consumption rate and a default time period; and when a sum of the long-term load and a current load of a second queue of the task queue is not smaller than the load alert level, deploying a microservice corresponding to the second queue at a second available edge host.

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.