Abstract: The present disclosure discloses a virtual memory management method and apparatus supporting physical addresses larger than virtual addresses. The method comprises steps of: determining a target virtual address corresponding to an instruction fetch address or a load storage address in any one of a user mode, a supervisor mode, or a machine mode; determining a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, the virtual memory management unit being internally provided with page table entries that map virtual addresses to physical addresses, the bit width of the target virtual address being possibly less than or equal to that of the target physical address, particularly in a many-core application field; and finally, returning the target physical address to a corresponding instruction fetch unit or load memory unit, thereby ensuring the correctness and validity.

Abstract: Embodiments of the present application provide a processing method and apparatus for defending against shared storage side channel attacks, an electronic device and a computer-readable storage medium, and relate to the technical field of computers. In the embodiment of the present application, first time information is acquired by a clock thread, and the first time information is obfuscated to obtain second time information; and, the second time information is transmitted to an attack thread by a clock thread. Since the second time information acquired by the attack thread is obfuscated, that is, the second time information is inaccurate, the attack thread cannot successfully complete a side channel attack when it performs side channel attacks based on the inaccurate time information, so that the system can be protected.

Abstract: The present invention relates to a prefabricated infilled panel-frame structure capable of accommodating seismic-loading and seismic energy dissipation, and a construction method thereof, including a frame body, a prefabricated infilled panel group, a panel connector, and a disc spring assembly. During an earthquake, the present invention slides to dissipate energy only after the maximum starting sliding force is exceeded, thus providing the structure with a relatively high lateral stiffness prior to sliding. After an earthquake, the disc spring assembly of the present invention may provide a certain restoring force due to being compressed so as to reduce the residual displacement. Further, the present invention achieves the bidirectional deformation cooperation of the prefabricated infilled panel under earthquakes, so that the infilled panel may still achieve the function of seismic energy dissipation under the coupling action of in-plane and out-of-plane loads.

Abstract: A BMS sleep wake-up circuit and method, a BMS, and an electric device are provided. The BMS sleep wake-up circuit is provided with an enabling circuit. When a charging device is connected, in response to the charging device being plugged in, the enabling circuit generates an enabling level to wake up a BMS, and outputs a self-locking signal through a control circuit, so that a wake-up chip keeps the BMS awake. Additionally, under the condition that the charging device remains plugged in, after the self-locking signal is canceled, the wake-up chip is turned off, so that the BMS can enter a sleeping state.

Abstract: This application discloses a BMS sleep wake-up circuit and method, a BMS, and an electric device. The BMS sleep wake-up circuit is provided with an enabling circuit. When a charging device is plugged in, the wake-up chip can be enabled through a first enabling signal to activate to wake up a BMS, and a control circuit outputs a self-locking signal, so that the wake-up chip keeps waking up the BMS. Additionally, after being activated, a mode in which the wake-up chip is enabled to activate is changed to a mode in which the wake-up chip is enabled through a second enabling signal to activate to wake up the BMS, so that when the charging device remains plugged in, after the self-locking signal is canceled, the wake-up chip is turned off, allowing the BMS to enter a sleeping state.

Abstract: An apparatus for defending against control flow attack, including: a key acquisition module, configured to acquire response data, which is output by a physical unclonable function PUF module to an input stimulus, and store the response data in a register as key data to be used; an encryption module, configured to encrypt target execution data in a program control flow based on the key data in the process of the processor executing the program control flow, the target execution data including at least one of a target instruction at an indirect jump destination address and a function call return address; a decryption module, configured to decrypt the encrypted target execution data when the processor is to execute the target execution data; and an execution module, configured to continue to execute the program control flow based on the decrypted target execution data.

Abstract: This application discloses a switched-mode power supply including a voltage isolation module, a voltage regulator module, a voltage converter circuit, a first switch, and an electric vehicle battery monitoring module; the voltage isolation module has an input connected to an electric vehicle battery and an output connected to an input terminal of the voltage regulator module. An output terminal of the voltage regulator module is connected to an input terminal of the voltage converter circuit, an output terminal of the voltage converter circuit is connected to one terminal of the first switch, and another terminal of the first switch is connected to the electric vehicle battery monitoring module; and when the switched-mode power supply is in a low-power state, the first switch turns on and off intermittently according to a clock signal received, so that the electric vehicle battery monitoring module monitors the electric vehicle battery intermittently.

Abstract: The present invention relates to a prefabricated infilled panel-frame structure capable of accommodating seismic-loading and seismic energy dissipation, and a construction method thereof, including a frame body, a prefabricated infilled panel group, a panel connector, and a disc spring assembly. During an earthquake, the present invention slides to dissipate energy only after the maximum starting sliding force is exceeded, thus providing the structure with a relatively high lateral stiffness prior to sliding. After an earthquake, the disc spring assembly of the present invention may provide a certain restoring force due to being compressed so as to reduce the residual displacement. Further, the present invention achieves the bidirectional deformation cooperation of the prefabricated infilled panel under earthquakes, so that the infilled panel may still achieve the function of seismic energy dissipation under the coupling action of in-plane and out-of-plane loads.

Abstract: The present application relates to a modified immune effector cell, wherein the functions of a T cell antigen receptor (TCR) and major histocompatibility complexes (MHCI, MHCII) in the modified immune effector cell are inhibited in a T cell, and the modified immune effector cell comprises a chimeric antigen receptor (CAR) targeting IL13R?2. The modified immune effector cell of the present application knocks out TCR and HLA-A genes expressed by the cell while recognizing surface antigens of tumor cells, so that multiple effects of improving the anti-tumor effect of CAR-T cells, prolonging the survival time of the cells, and reducing the immune rejection response caused by allogeneic cell therapy are achieved.

Abstract: The present application relates to an antigen-binding polypeptide that specifically binds to B7H3, comprising at least one complementarity-determining region (CDR) of an antibody heavy chain variable region (VH), wherein the VH comprises an amino acid sequence set forth in SEQ ID NO: 25. The present application further relates to a chimeric antigen receptor comprising the antigen-binding polypeptide and a universal CAR-T cell comprising the chimeric antigen receptor. The CAR-T cell recognizes a surface antigen of a tumor cell and knocks out TCR and HLA-A genes expressed by the cell at the same time, so that the immune rejection caused by an allogeneic CAR-T therapy is reduced, the survival time of the cell is prolonged, and the anti-tumor effect is improved.

Abstract: The present application relates to an antigen-binding polypeptide that specifically binds to B7H3, comprising at least one complementarity-determining region (CDR) of an antibody heavy chain variable region (VH), wherein the VH comprises an amino acid sequence set forth in SEQ ID NO: 25. The present application further relates to a chimeric antigen receptor comprising the antigen-binding polypeptide and a universal CAR-T cell comprising the chimeric antigen receptor. The CAR-T cell recognizes a surface antigen of a tumor cell and knocks out TCR and HLA-A genes expressed by the cell at the same time, so that the immune rejection caused by an allogeneic CAR-T therapy is reduced, the survival time of the cell is prolonged, and the anti-tumor effect is improved.

Abstract: A method for preparing an inorganic perovskite battery based on a synergistic effect of gradient annealing and antisolvent includes preparing a perovskite layer by a gradient annealing and an antisolvent treatment. A thickness of the perovskite layer is 100 to 1000 nm; when preparing a perovskite precursor solution of the perovskite layer, a solvent is an amide-based solvent and/or a sulfone-based solvent; a concentration of the perovskite precursor solution for preparing the perovskite layer is 0.4 to 2 M; and the gradient annealing is conducted at 40 to 70° C./0.5 to 5 min+70 to 130° C./0.5 to 5 min+130 to 160° C./5 to 20 min+160 to 280° C./0 to 20 min; and a solvent for the anti-solvent treatment is an alcohol solvent, a benzene solvent or an ether solvent.

Abstract: The present invention provides a display device and a control method thereof. The display device includes a display panel and a voltage processing module. The display panel includes a common electrode and a plurality of data lines; wherein the voltage processing module is connected to the common electrode to determine a difference between a common voltage signal in an nth frame and a standard voltage, and is connected to at least one of the common electrode and the plurality of data lines, and controls a voltage of the at least one of the common electrode and the plurality of data lines in an (n+k)th frame, wherein both n and k are positive integers.

Abstract: The present invention provides a display device and a control method thereof. The display device includes a display panel and a voltage processing module. The display panel includes a common electrode and a plurality of data lines; wherein the voltage processing module is connected to the common electrode to determine a difference between a common voltage signal in an nth frame and a standard voltage, and is connected to at least one of the common electrode and the plurality of data lines, and controls a voltage of the at least one of the common electrode and the plurality of data lines in an (n+k)th frame, wherein both n and k are positive integers.

Abstract: The present disclosure discloses a virtual memory management method and apparatus supporting physical addresses larger than virtual addresses. The method comprises steps of: determining a target virtual address corresponding to an instruction fetch address or a load storage address in any one of a user mode, a supervisor mode, or a machine mode; determining a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, the virtual memory management unit being internally provided with page table entries that map virtual addresses to physical addresses, the bit width of the target virtual address being possibly less than or equal to that of the target physical address, particularly in a many-core application field; and finally, returning the target physical address to a corresponding instruction fetch unit or load memory unit, thereby ensuring the correctness and validity.

Abstract: The present disclosure provides a spiral blade, a grinding component and a food processor. The spiral blade includes: a spiral blade body, and the spiral blade body includes a feeding area used for feeding, a grinding area connected with the feeding area and a discharging area connected with the grinding area; and a plurality of spiral ribs are arranged on the grinding area, and a cleaning structure is arranged on the discharging area. The spiral blade is applied to the food processor and is only used for grinding food rather than extruding juice and discharging residues, therefore its structure is relatively simple, meanwhile, as a cleaning structure is arranged on the discharging area, the cleaning structure can be used for pushing the crushed food to a predetermined area.

Abstract: An apparatus for defending against control flow attack, including: a key acquisition module, configured to acquire response data, which is output by a physical unclonable function PUF module to an input stimulus, and store the response data in a register as key data to be used; an encryption module, configured to encrypt target execution data in a program control flow based on the key data in the process of the processor executing the program control flow, the target execution data including at least one of a target instruction at an indirect jump destination address and a function call return address; a decryption module, configured to decrypt the encrypted target execution data when the processor is to execute the target execution data; and an execution module, configured to continue to execute the program control flow based on the decrypted target execution data.

Abstract: Embodiments of the present application provide a processing method and apparatus for defending against shared storage side channel attacks, an electronic device and a computer-readable storage medium, and relate to the technical field of computers. In the embodiment of the present application, first time information is acquired by a clock thread, and the first time information is obfuscated to obtain second time information; and, the second time information is transmitted to an attack thread by a clock thread. Since the second time information acquired by the attack thread is obfuscated, that is, the second time information is inaccurate, the attack thread cannot successfully complete a side channel attack when it performs side channel attacks based on the inaccurate time information, so that the system can be protected.