Abstract: Embodiments provide a storage system, including: a basis chip and memory chips, where the memory chip includes memory cells, the storage system has channels, each of the channels includes a partial number of memory cells in all the memory chips, a partial region of each of the channels corresponds to one memory chip, and each channel is electrically connected to the basis chip; and a temperature processing circuit configured to obtain first temperature codes corresponding to the memory chips, to obtain a second temperature code representing a temperature of the basis chip, and to compare the first temperature codes with the second temperature code to output a high temperature representation code, where the first temperature code represents a maximum temperature in the partial regions of all the channels, and the high temperature representation code is one of the first temperature codes or the second temperature code representing a higher temperature.

Abstract: A circuit for through silicon via (TSV) detection includes a TSV to be tested, an equivalent adjustable resistor and a reverse output circuit. A first terminal of the TSV to be tested is connected to a second terminal of the equivalent adjustable resistor, and a second terminal of the TSV to be tested is grounded. An input terminal of the reverse output circuit is connected to the first terminal of the TSV to be tested. The method includes: adjusting a resistance value of the equivalent adjustable resistor to a preset first resistance value, and keeping a voltage of a first terminal of the equivalent adjustable resistor at a preset voltage value, the first resistance value is a maximum resistance value of an equivalent resistor corresponding to the TSV to be tested when the TSV to be tested is normal.

Abstract: The present disclosure relates to a method for ground travel collision avoidance of an aircraft, comprising: sensing, by a sensing module mounted on a towing vehicle for the aircraft, an object in a surrounding environment of the aircraft; determining whether the object is secure based on a contour feature of the aircraft and a relative position relation between the object and the aircraft; and implementing a collision avoidance measure in response to determining that the object is insecure. The present disclosure also relates to a system and a device for ground travel collision avoidance of an aircraft.

Abstract: A memory array detection circuit includes: a memory array including multiple memory cells; a write circuit, connected to the memory array and configured to write same initial data into each memory cell of the memory array; a read circuit, connected to the memory array and configured read the data stored in each memory cell of the memory array; and a data compression circuit, connected to the read circuit and configured to: compare the data read from the multiple memory cells, and detect whether the memory array is defective according to whether the read data are identical.

Abstract: A sense amplifier, a control method of the sense amplifier, and a memory are provided. The sense amplifier includes: a first power input terminal, a second power input terminal, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a first negative-channel metal-oxide semiconductor (NMOS) transistor, a second NMOS transistor, a first positive-channel metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor.

Abstract: A sense amplifier includes a first power terminal, a second power terminal, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor. When the sense amplifier works, by outputting appropriate sequential logic signals to the four switching units respectively, controlling the on and off of the four switching units.

Abstract: Embodiments provide a storage system, including: a basis chip and memory chips, where the memory chip includes memory cells, the storage system has channels, each of the channels includes a partial number of memory cells in all the memory chips, a partial region of each of the channels corresponds to one memory chip, and each channel is electrically connected to the basis chip; and a temperature processing circuit configured to obtain first temperature codes corresponding to the memory chips, to obtain a second temperature code representing a temperature of the basis chip, and to compare the first temperature codes with the second temperature code to output a high temperature representation code, where the first temperature code represents a maximum temperature in the partial regions of all the channels, and the high temperature representation code is one of the first temperature codes or the second temperature code representing a higher temperature.

Abstract: A sense amplifier includes a first power terminal, a second power terminal, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor. When the sense amplifier works, by outputting appropriate sequential logic signals to the four switching units respectively, controlling the on and off of the four switching units.

Abstract: A memory array detection circuit includes: a memory array including multiple memory cells; a write circuit, connected to the memory array and configured to write same initial data into each memory cell of the memory array; a read circuit, connected to the memory array and configured read the data stored in each memory cell of the memory array; and a data compression circuit, connected to the read circuit and configured to: compare the data read from the multiple memory cells, and detect whether the memory array is defective according to whether the read data are identical.

Abstract: A circuit for through silicon via (TSV) detection includes a TSV to be tested, an equivalent adjustable resistor and a reverse output circuit. A first terminal of the TSV to be tested is connected to a second terminal of the equivalent adjustable resistor, and a second terminal of the TSV to be tested is grounded. An input terminal of the reverse output circuit is connected to the first terminal of the TSV to be tested. The method includes: adjusting a resistance value of the equivalent adjustable resistor to a preset first resistance value, and keeping a voltage of a first terminal of the equivalent adjustable resistor at a preset voltage value, the first resistance value is a maximum resistance value of an equivalent resistor corresponding to the TSV to be tested when the TSV to be tested is normal.

Abstract: A bandgap voltage reference core circuit includes: a generating circuit, a first voltage dividing circuit and a second voltage dividing circuit. The generating circuit is configured to generate a positive temperature coefficient voltage and a negative temperature coefficient voltage, and obtain a positive temperature coefficient current and a negative temperature coefficient current based on the positive temperature coefficient voltage and the negative temperature coefficient voltage. The first voltage dividing circuit is connected to the generating circuit and the second voltage dividing circuit respectively, and is configured to generate an initial current based on the positive temperature coefficient current and the negative temperature coefficient current. The second voltage dividing circuit is configured to determine a reference voltage based on the initial current. The first voltage dividing circuit and the second voltage dividing circuit affect a voltage dividing proportion of the reference voltage.

Abstract: The present disclosure relates to a sense amplifier, a control method of the sense amplifier, and a memory. The sense amplifier includes: a first power input terminal, a second power input terminal, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a first negative-channel metal-oxide semiconductor (NMOS) transistor, a second NMOS transistor, a first positive-channel metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor.