Patents by Inventor Weijie Yu

Weijie Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240190712
    Abstract: The invention provides a nano-silicon agglomerate composite negative electrode material of pine needle and branch-shaped three-dimensional network structure and a method for preparing the same. The nano-silicon agglomerate composite negative electrode material comprises nano-sized core particles, a nano-silicon agglomerate of pine needle and branch-shaped three-dimensional network structure growing around the nano-sized core particles, and a composite coating layer over the nano-silicon agglomerate of needles and branch-shaped three-dimensional network structure. With measurements, it is shown that the nano-silicon agglomerate composite negative electrode material, when being applied in lithium ion battery, has excellent battery charge-discharge cycle performances and rate capability, and it has an initial discharge capacity per gram of more than 2600 mAh/g, and an initial coulombic efficiency of no less than 85%.
    Type: Application
    Filed: August 3, 2021
    Publication date: June 13, 2024
    Applicant: TOMI(CHENGDU) APPLIED TECHNOLOGY RESEARCH INSTITUTE COMPANY LIMITED
    Inventors: Weijie YU, Si-Chung CHANG, Fusheng LI, Chang ZHAO, Xuezhi DAI, Xiaobing CHEN, Yang YU
  • Patent number: 10747659
    Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a memory controller or similar device for storing sequential image data or other data streams composed of pages of data. In one example, the memory controller compares data within current and previous image frames on a page-by-page basis. If a pair of pages match, the memory controller creates a link between the two pages so the duplicate page need not be stored. During a subsequent read operation, the flash controller accesses stored links to identify the physical storage addresses of any matching pages stored in connection with a previous frame to permit efficient retrieval. In some examples, a page is compared with both the previous corresponding page and with the neighboring pages of that previous page. Exemplary read, write and erase operations are described herein using the links.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Weijie Yu, Rohit Sehgal, Zachary David Shepard
  • Publication number: 20190243754
    Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a memory controller or similar device for storing sequential image data or other data streams composed of pages of data. In one example, the memory controller compares data within current and previous image frames on a page-by-page basis. If a pair of pages match, the memory controller creates a link between the two pages so the duplicate page need not be stored. During a subsequent read operation, the flash controller accesses stored links to identify the physical storage addresses of any matching pages stored in connection with a previous frame to permit efficient retreival. In some examples, a page is compared with both the previous corresponding page and with the neighboring pages of that previous page. Exemplary read, write and erase operations are described herein using the links.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 8, 2019
    Inventors: Weijie Yu, Rohit Sehgal, Zachary David Shepard
  • Publication number: 20100117878
    Abstract: A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC having a gain setting that controls a magnitude of the digital representations. The ADC further includes correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to adjust the gain settings of the component ADCs and/or phase angles of the timing signals based on gain and phase errors indicated by the FFTs.
    Type: Application
    Filed: January 21, 2010
    Publication date: May 13, 2010
    Inventors: Samuel Sheng, Weijie Yu