Abstract: An energy storage device and a method thereof are provided. The power transfer circuit transfers a DC voltage provided by a battery module into an AC output voltage to provide the AC output voltage to an output end of the power transfer circuit for providing power to a load. When the AC output voltage is at a default phase, the power transfer circuit is disabled in a default period, and whether the energy storage device may be shut down is determined according to a voltage difference of the AC output voltage sensed by a sensing circuit during the default period.

Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A semiconductor structure includes a substrate, a piezoelectric layer, and a stress structure. The substrate includes a first surface and a second surface, wherein a portion of the substrate proximal to the first surface defines a diaphragm. The piezoelectric layer is disposed over the first surface of the substrate and surrounds the diaphragm, wherein the piezoelectric layer includes a first portion and a second portion arranged along a periphery of the diaphragm from a top view. The stress structure includes a plurality of dielectric layers disposed over the piezoelectric layer and between the substrate and the piezoelectric layer, and a total thickness of a first portion of the stress structure overlapping the first portion of the piezoelectric layer is different from a total thickness of a second portion of the stress structure overlapping the second portion of the piezoelectric layer. A method for manufacturing a semiconductor structure is also provided.

Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

Abstract: An electronic package and the manufacturing method thereof are provided, in which a first electronic element and a second electronic element are disposed on a carrier structure, and the first electronic element and the second electronic element are electrically connected to each other by a wire. Therefore, by replacing some layers of the circuit layer of the carrier structure with the wire, the carrier structure can satisfy the functional signal transmission of the first and second electronic elements without configuring too many circuit layers, so as to shorten the process steps and time of the carrier structure, thereby effectively reducing the manufacturing cost of the electronic package.

Abstract: A light-emitting device includes a substrate, a light-emitting diode, a first layer, a color filter layer, and a second layer. The light-emitting diode is disposed on the substrate. The first layer is disposed on the substrate and has an opening. At least a portion of the light-emitting diode is disposed in the opening of the first layer. The color filter layer is disposed on the light-emitting diode. The second layer is disposed on the first layer and has an opening overlapped with the opening of the first layer. The second layer is configured to shield light emitted from the light-emitting diode. In the cross-sectional view of the light-emitting device, the minimum width of the opening of the first layer is less than the minimum width of the opening of the second layer.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: A multi-level digital step attenuator (DSA) with a hybrid attenuation circuit is shown. The hybrid attenuation circuit is coupled between an input node and an output node of the multi-level DSA. The bypass switch of the multi-level DSA is controlled to provide a bypass path between the input node and the output node of the of the multi-level DSA when the hybrid attenuation circuit is in a disabled state. In the first active state, the hybrid attenuation circuit is switched to form a T-type structure to provide a first amount of signal attenuation. In the second active state, the hybrid attenuation circuit is switched to form a Pi-type structure to provide a second amount of signal attenuation.

Abstract: A digital step attenuator (DSA) with efficient high-frequency signal attenuation is shown. The DSA has an attenuation circuit, a bypass switch, and a diversion circuit. The attenuation circuit is coupled between an input node and an output node of the digital step attenuator. The bypass switch is controlled by a bypass control signal to provide a bypass path between the input node and the output node of the digital step attenuator. The diversion circuit couples a control terminal of the bypass switch to a ground terminal in response to the bypass control signal being in an inactive state.

Abstract: A hidden shackle style lock is disclosed. The lock has a substantially cylindrical housing having a top surface, a bottom surface, and a curved side surface. The lock also has a first cavity on the bottom surface of the housing which extends part way along a thickness of the housing, and a second cavity on the side surface intersecting with the first cavity. The lock further includes has a hollow sleeve slidably attached within the second cavity. The sleeve has a first end face, a second end face, and a third cavity. The third cavity extends from the first end face to the second face and is substantially coaxial with the second cavity. A shackle is coupled to the first end face of the sleeve. A core member with a locking mechanism is disposed within the third cavity and coupled to the shackle. A driver member is located between the core member and the shackle and couples the core member to the shackle.

Abstract: A hidden shackle style lock is disclosed. The lock includes a substantially cylindrical housing having a top surface, a bottom surface, and a curved side surface. The lock also includes a first cavity on the bottom surface of the housing extending part way along a thickness of the housing, and a second cavity on the side surface intersecting with the first cavity. A hollow sleeve is slidably attached within the second cavity. The sleeve includes a first end face, a second end face, and a third cavity. The third cavity extends from the first end face to the second face and is substantially coaxial with the second cavity. A shackle having a first end and a second end is fixedly coupled to the first end face of the sleeve. The lock also includes an interchangeable core having a first locking mechanism and a second locking mechanism lockingly disposed within the third cavity, and coupled to the straight shackle.

Abstract: A surgical clamp includes first and second supports respectively having first and second engagement sections. The first and second supports are pivotably connected at a connection by a pivotal portion such that the first and second supports are pivotable about a pivot axis extending through the connection. An opening is defined between the first and second engagement sections for receiving a bone of a patient. A connecting tube includes a first end fixed to the connection. A guiding tube includes an end connected to a second end of the connecting tube and is located in a central plane of the opening between the first and second engagement sections. The central plane includes the pivot axis and has equal spacing to the first and second engagement sections. A sliding rod is fixed to the connecting tube and includes a sliding groove slideably receiving a pole located on the pivotal portion.

Abstract: A bone anchor comprises a screw body and a flange, which are joined together in a way to keep their rotation independent from each other. In implanting the screw body into a bone, the flange does not rotate to prevent twisting and/or snarling of the suture in wounded bone from occurring.

Abstract: A surgical clamp includes first and second supports respectively having first and second engagement sections. The first and second supports are pivotably connected at a connection by a pivotal portion such that the first and second supports are pivotable about a pivot axis extending through the connection. An opening is defined between the first and second engagement sections for receiving a bone of a patient. A connecting tube includes a first end fixed to the connection. A guiding tube includes an end connected to a second end of the connecting tube and is located in a central plane of the opening between the first and second engagement sections. The central plane includes the pivot axis and has equal spacing to the first and second engagement sections. A sliding rod is fixed to the connecting tube and includes a sliding groove slideably receiving a pole located on the pivotal portion.

Abstract: The invention discloses a semiconductor light-emitting device and a fabricating method thereof. The semiconductor light-emitting device according to the invention includes a substrate, a multi-layer structure, a top-most layer, and at least one electrode. The multi-layer structure is formed on the substrate and includes a light-emitting region. The top-most layer is formed on the multi-layer structure, and the lower part of the sidewall of the top-most layer exhibits a first surface morphology relative to a first pattern. In addition, the upper part of the sidewall of the top-most layer exhibits a second surface morphology relative to a second pattern. The first pattern is different from the second pattern. The at least one electrode is formed on the top-most layer.

Abstract: A high efficiency lighting device comprising a light emitting diode structure, an eutectic layer and a distributed-Bragg reflecting layer (DBR) therebetween is disclosed. The distributed-Bragg reflecting layer is attached to said light emitting diode structure by vapor deposition and comprises a plurality of high refraction layers, a plurality of low refraction layers and a micro-contact layer array. The high refraction layers and said low refraction layers are arranged in an alternating manner, so as to form a stacked thin film having an alternate high/low refraction pattern. The micro-contact layers are in said stacked thin film and extend vertically through the stacked thin film, therefore connecting said light emitting diode structure and said eutectic layer.